MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 74

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 2-80:
REGISTER 2-81:
DS39776C-page 74
MRF24J40
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-2
bit 1-0
Note 1:
STARTCNT
MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16
R/W-0
W-0
Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and
Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and
Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
STARTCNT: Start Sleep Mode Counters bits
1 = Trigger Sleep mode for Nonbeacon Enable mode (BO = 0xF and Slotted = 0). Bit automatically clears
Reserved: Maintain as ‘0’
MAINCNT<25:24>: Main Counter bits
Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI) and
inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units:
SLPCLK.
MAINCNT<23:16>: Main Counter bits
Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI)
and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices.
Units: SLPCLK.
R/W-0
to ‘0’.
R/W-0
r
MAINCNT2: MAIN COUNTER 2 REGISTER (ADDRESS: 0x228)
MAINCNT3: MAIN COUNTER 3 REGISTER (ADDRESS: 0x229)
(1)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
(1)
R/W-0
R/W-0
r
R/W-0
R/W-0
r
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
r
R/W-0
R/W-0
r
R/W-0
x = Bit is unknown
MAINCNT25
© 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
MAINCNT24
R/W-0
R/W-0
bit 0
bit 0