MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 128

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.17
The MRF24J40 provides a hardware security engine
that implements the Advanced Encryption Standard,
128-bit (AES-128) according to the IEEE 802.15.4-2003
Standard. The MRF24J40 supports seven security
suites which provide a group of security operations
designed to provide security services on MAC and upper
layer frames.
• AES-CTR
• AES-CCM-128
• AES-CCM-64
• AES-CCM-32
• AES-CRC-MAC-128
• AES-CRC-MAC-64
• AES-CRC-MAC-32
Security keys are stored in the Security Key FIFO. Four
security keys, three for encryption and one for decryption,
are stored in the memory locations shown in Figure 3-20.
The security engine can be used for the encryption and
decryption of MAC sublayer frames for transmission
and reception of secured frames and provide security
encryption and decryption services to the upper layers.
These functions are described in the following
subsections.
3.17.1
A frame can be encrypted and transmitted from each of
the TX FIFOs. Table 3-23 lists the TX FIFO and associ-
ated security key memory address and control register
bits.
TABLE 3-23:
DS39776C-page 128
MRF24J40
TX Normal FIFO
TX GTS1 FIFO
TX GTS2 FIFO
TX Beacon FIFO
Note:
TX FIFO
Security
MAC SUBLAYER TRANSMIT
ENCRYPTION
The TX GTS2 FIFO and TX Beacon FIFO share the same security key memory location.
ENCRYPTION SECURITY KEY AND CONTROL REGISTER BITS
Memory Address
Security Key
0x2A0-0x2AF
0x2A0-0x2AF
0x280-0x28F
0x290-0x29F
(SECCON0 0x2C<2:0>)
(SECCON1 0x2D<6:4>)
(SECCR2 0x37<2:0>)
(SECCR2 0x37<5:3>)
Security Suite
TXG1CIPHER
TXG2CIPHER
TXNCIPHER
TXBCIPHER
Select Bits
Preliminary
FIGURE 3-20:
Note:
0x2A0
0x2AF
0x2B0
0x2BF
0x280
0x28F
0x290
0x29F
(TXG1CON 0x1C<1>)
(TXG2CON 0x1D<1>)
Security Enable Bits
(TXNCON 0x1B<1>)
(TXBCON 0x1A<1>)
TXBCNSECEN
TXG1SECEN
TXG2SECEN
TXNSECEN
The TX GTS2 FIFO and TX Beacon FIFO
share the same security key memory
location.
TX Beacon FIFO
TX Normal FIFO
TX GTS2 FIFO/
Memory Space
TX GTS1 FIFO
Long Address
Security Key
Security Key
Security Key
Security Key
RX FIFO
MEMORY MAP OF
SECURITY KEY FIFO
© 2010 Microchip Technology Inc.
(TXG1CON 0x1C<0>)
(TXG2CON 0x1D<0>)
(TXNCON 0x1B<0>)
(TXBCON 0x1A<0>)
TXBCNTRIG
Trigger Bit
TXG1TRIG
TXG2TRIG
TXNTRIG
16 bytes
16 bytes
16 bytes
16 bytes