ATMEGA165P-16ANR Atmel, ATMEGA165P-16ANR Datasheet - Page 126
![IC MCU AVR 16K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA165P-16ANR
Manufacturer Part Number
ATMEGA165P-16ANR
Description
IC MCU AVR 16K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15. Timer/Counter0 and Timer/Counter1 Prescalers
15.1
15.2
15.3
15.4
8019K–AVR–11/10
Overview
Prescaler Reset
Internal Clock Source
External Clock Source
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counter1 and
Timer/Counter0.
The prescaler is free running, that is, operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn[2:0] > 1). The number of system
clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-
tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
as a clock source. The prescaled clock has a frequency of either f
f
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (
is transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn[2:0] = 6) edge it detects.
Figure 15-1. T1/T0 Pin Sampling
CLK_I/O
Tn
clk
T1
I/O
/clk
/256, or f
T0
). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
D
LE
CLK_I/O
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be used
T1
/clk
T
0
pulse for each positive (CSn[2:0] = 7) or negative
D
Q
ATmega165P
CLK_I/O
Edge Detector
clk
/8, f
I/O
Figure 15-1
). The latch
CLK_I/O
Tn_sync
(To Clock
Select Logic)
/64,
126
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