ATMEGA165P-16ANR Atmel, ATMEGA165P-16ANR Datasheet - Page 162
![IC MCU AVR 16K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA165P-16ANR
Manufacturer Part Number
ATMEGA165P-16ANR
Description
IC MCU AVR 16K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
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18.3.2
18.3.3
8019K–AVR–11/10
Double Speed Operation (U2Xn)
External Clock
Table 18-1.
Note:
Some examples of UBRR values for some system clock frequencies are found in
page
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
Operating Mode
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
179.
BAUD
f
UBRR
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps)
osc
depends on the stability of the system clock source. It is therefore recommended to
Equations for Calculating Baud Rate Register Setting
Figure 18-2 on page 161
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
Equation for Calculating Baud
BAUD
BAUD
BAUD
=
=
=
Rate
-------------------------------------- -
16 UBRR
---------------------------------- -
8 UBRR
---------------------------------- -
2 UBRR
f
for details.
XCK
(
(
(
(1)
f
f
f
<
OSC
OSC
OSC
f
---------- -
OSC
4
+
+
+
1
1
1
)
)
)
Equation for Calculating UBRR
UBRR
UBRR
UBRR
ATmega165P
=
=
=
Value
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
Table 18-4 on
–
–
–
162
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