ATMEGA165P-16ANR Atmel, ATMEGA165P-16ANR Datasheet - Page 235
![IC MCU AVR 16K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA165P-16ANR
Manufacturer Part Number
ATMEGA165P-16ANR
Description
IC MCU AVR 16K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
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23.5.2
23.5.3
8019K–AVR–11/10
Scanning the RESET Pin
Scanning the Clock Pins
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 23-5. Observe-only Cell
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 23-6
The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-
put is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
Oscillator does not have external connections.
Figure 23-6. Boundary-scan Cells for Oscillators and Clock Options
From Digital Logic
shows how each Oscillator with external connection is supported in the scan chain.
Previous
From
Cell
ShiftDR
0
1
From System Pin
ClockDR
D
UpdateDR
Q
Next
Cell
To
D
G
Previous
From
Cell
Q
ShiftDR
EXTEST
0
1
0
1
XTAL1/TOSC1
ClockDR
ENABLE
Oscillator
D
FF1
Q
XTAL2/TOSC2
OUTPUT
Next
Cell
To
To System Logic
Previous
From
Cell
ShiftDR
0
1
ClockDR
ATmega165P
D
FF1
Q
Next
Cell
To
Figure 23-5
To System Logic
235
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