ATMEGA165P-16ANR Atmel, ATMEGA165P-16ANR Datasheet - Page 20
![IC MCU AVR 16K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA165P-16ANR
Manufacturer Part Number
ATMEGA165P-16ANR
Description
IC MCU AVR 16K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8019K–AVR–11/10
The following procedure should be followed when writing the EEPROM (the order of steps 3 and
4 is not essential). See
register bit:
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See
Support – Read-While-Write Self-Programming” on page 250
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,
the CPU is halted for two cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses.
gramming time for EEPROM access from the CPU.
Table 6-1.
The following code examples show one assembly and one C function for writing to the
EEPROM. To avoid that interrupts will occur during execution of these functions, the examples
assume that interrupts are controlled (for example by disabling interrupts globally). The exam-
ples also assume that no Flash Boot Loader is present in the software. If such code is present,
the EEPROM write function must also wait for any ongoing SPM command to finish.
Symbol
EEPROM write (from CPU)
EEPROM Programming Time
“Register Description” on page 24
Number of Calibrated
RC Oscillator Cycles
27 072
for supplementary description for each
Table 6-1
Typical Programming Time
ATmega165P
for details about Boot
lists the typical pro-
3.3 ms
“Boot Loader
20
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