S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 139

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3.2.7
Read: Anytime
Write: Anytime
These eight index bits are used to page 1KB blocks into the Data FLASH page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see
accessing up to 256KB of Data FLASH (in the Global map) within the 64KB Local map. The Data FLASH
page index register is effectively used to construct paged Data FLASH addresses in the Local map format.
Freescale Semiconductor
Address: 0x0017
Reset
EP[7:0]
Field
7–0
W
R
EP7
0
Data FLASH Page Index Bits 7–0 — These page index bits are used to select which of the 256 Data FLASH
array pages is to be accessed in the Data FLASH Page Window.
Data FLASH Page Index Register (EPAGE)
1
7
0
EP6
1
Figure 3-15. Data FLASH Page Index Register (EPAGE)
1
6
0
S12XS Family Reference Manual, Rev. 1.11
Figure 3-16. EPAGE Address Mapping
Table 3-9. EPAGE Field Descriptions
0
EP5
1
5
Bit17
Global Address [22:0]
Bit16
EPAGE Register [7:0]
EP4
1
4
Description
EP3
1
3
Bit10
Address: CPU Local Address
Bit9
EP2
Memory Mapping Control (S12XMMCV4)
or BDM Local Address
1
2
Figure
Address [9:0]
3-16). This supports
EP1
1
1
Bit0
EP0
0
0
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