S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 516

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

256 KByte Flash Module (S12XFTMR256K1V1)
18.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
516
FDIV[6:0]
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
0x0010
0x0011
0x0012
0x0013
FRSV2
FRSV3
FRSV4
Field
FOPT
6–0
7
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms.
Please refer to
Flash Clock Divider Register (FCLKDIV)
0
7
W
W
W
W
R
R
R
R
NV7
= Unimplemented or Reserved
7
0
0
0
Figure 18-4. FTMR256K1 Register Summary (continued)
Section 18.4.1, “Flash Command Operations,”
0
6
Figure 18-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
NV6
Table 18-7
6
0
0
0
Table 18-6. FCLKDIV Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
0
5
shows recommended values for FDIV[6:0] based on OSCCLK frequency.
NV5
5
0
0
0
0
4
NV4
Description
4
0
0
0
FDIV[6:0]
0
3
for more information.
NV3
3
0
0
0
0
2
NV2
2
0
0
0
Freescale Semiconductor
NV1
0
1
1
0
0
0
NV0
0
0
0
0
0
0