S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 54

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Overview S12XS Family
1.6.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section.
1.6.3.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.3
Refer to the PIM section for reset configurations of all peripheral module ports.
1.6.3.4
The RAM arrays are not initialized out of reset.
1.6.3.5
The COP time-out rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded from the Flash
register FOPT. See
configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP time-out rate is always set to the longest period (CR[2:0] = 111) after any
reset into Special Single Chip mode.
54
Flash Configuration Reset Sequence Phase
Reset While Flash Command Active
I/O Pins
Memory
COP Configuration
Table 1-11
FOPT Register
FOPT Register
and
NV[2:0] in
Table 1-11. Initial COP Rate Configuration
NV[3] in
Table 1-12. Initial WCOP Configuration
S12XS Family Reference Manual, Rev. 1.11
000
001
010
011
100
101
110
111
Table 1-12
1
0
for coding. The FOPT register is loaded from the Flash
COPCTL Register
COPCTL Register
CR[2:0] in
WCOP in
111
110
101
100
011
010
001
000
0
1
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