S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 98

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
Port Integration Module (S12XSPIMV1)
2.3.35
2.3.36
98
Address 0x0251
Address 0x0252
Read: Anytime.
Write:Never, writes to this register have no effect.
Read: Anytime.
Write: Anytime.
Field
PTIM
Reset
Reset
7-0
W
W
R
R
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
DDRM7
PTIM7
Port M Input Register (PTIM)
Port M Data Direction Register (DDRM)
u
0
7
7
= Unimplemented or Reserved
DDRM6
PTIM6
u
0
6
6
Figure 2-34. Port M Data Direction Register (DDRM)
Table 2-31. PTIM Register Field Descriptions
Figure 2-33. Port M Input Register (PTIM)
S12XS Family Reference Manual, Rev. 1.11
DDRM5
PTIM5
u
0
5
5
DDRM4
PTIM4
u
0
4
4
Description
u = Unaffected by reset
DDRM3
PTIM3
3
u
3
0
DDRM2
PTIM2
u
0
2
2
Freescale Semiconductor
DDRM1
PTIM1
Access: User read/write
u
0
1
1
Access: User read
DDRM0
PTIM0
u
0
0
0
1
1