AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 273

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3-15 • Different Components Contributing to the Static Power Consumption in Fusion Devices
Parameter
P
P
P
P
P
P
P
P
P
DC1
DC2
DC3
DC4
DC5
DC6
DC7
DC8
DC9
Core static power contribution in
operating mode
Device static power contribution in
standby mode
Device static power contribution in
sleep mode
NVM static power contribution
Analog
contribution of ADC
Analog
contribution per Quad
Static contribution per input pin –
standard dependent contribution
Static contribution per input pin –
standard dependent contribution
Static contribution for PLL
Static Power Consumption of Various Internal Resources
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
The calculation should be repeated for each clock domain defined in the design.
•
•
•
•
•
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
The number of NVM blocks used in the design
The number of Analog Quads used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
page
Read rate and write rate to the RAM—guidelines are provided for typical applications in
Table 3-17 on page
Read rate to the NVM blocks
Block
Block
Definition
3-27.
3-27.
static
static
3-27.
power
power
VCC33A
VCC33A
VCC33A
VCC33A
Supply
Power
VCCI
VCCI
VCC
VCC
VCC
R e v i s i o n 1
1.5 V
3.3 V
3.3 V
1.5 V
3.3 V
3.3 V
1.5 V
AFS1500 AFS600 AFS250 AFS090
Device-Specific Static Contributions
18
See
See
Actel Fusion Family of Mixed Signal FPGAs
Table 3-12 on page 3-18
Table 3-13 on page 3-20
7.5
0.66
0.03
1.19
8.25
2.55
3.3
4.50
3.00
Table 3-16 on
Table 3-17 on
Units
mW
mW
mW
mW
mW
mW
mW
3- 23