AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 281

FPGA - Field Programmable Gate Array 600K System Gates

AFS600-PQG208

Manufacturer Part Number
AFS600-PQG208
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS600-PQG208

Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
95
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AFS600-PQG208
Manufacturer:
Actel
Quantity:
135
Part Number:
AFS600-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AFS600-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Total Static Power Consumption—P
Total Power Consumption—P
In operating mode, the total power consumption of the device is 174.39 mW:
In standby mode, the total power consumption of the device is limited to 0.66 mW:
In sleep mode, the total power consumption of the device drops as low as 0.03 mW:
Operating Mode
P
P
P
P
Standby Mode
P
P
Sleep Mode
P
P
P
P
P
P
P
P
P
P
STAT
DC8
STAT
STAT
STAT
STAT
STAT
STAT
TOTAL
TOTAL
TOTAL
TOTAL
TOTAL
TOTAL
TOTAL
TOTAL
Number of Quads used: N
Number of NVM blocks available (AFS600): N
Number of input pins used: N
Number of output pins used: N
)
= P
= 7.50 mW + (2 * 1.19 mW) + 8.25 mW + (4 * 3.30 mW) + (30 * 0.00) + (40 * 0.00)
= 31.33 mW
= P
= 0.03 mW
= P
= 0.03 mW
= P
= 143.06 mW + 31.33 mW
= 174.39 mW
= P
= 0.03 mW + 0.63 mW
= 0.66 mW
= P
= 0.03 mW
DC1
DC2
DC3
STAT
STAT
STAT
+ (N
+ P
+ P
+ P
NVM-BLOCKS
DYN
DYN
DYN
QUADS
* P
TOTAL
INPUTS
DC4
OUTPUTS
= 4
) + P
STAT
= 30
R e v i s i o n 1
DC5
= 40
+ (N
NVM-BLOCKS
QUADS
* P
DC6
Actel Fusion Family of Mixed Signal FPGAs
= 2
) + (N
INPUTS
* P
DC7
) + (N
OUTPUTS
3- 31
*

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