AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 30

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
2- 14
VersaNet Global Networks and Spine Access
The Fusion architecture contains a total of 18 segmented global networks that can access the
VersaTiles, SRAM, and I/O tiles on the Fusion device. There are 6 chip (main) global networks that
access the entire device and 12 quadrant networks (3 in each quadrant). Each device has a total of 18
globals. These VersaNet global networks offer fast, low-skew routing resources for high-fanout nets,
including clock signals. In addition, these highly segmented global networks offer users the flexibility to
create low-skew local networks using spines for up to 180 internal/external clocks (in an AFS1500
device) or other high-fanout nets in Fusion devices. Optimal usage of these low-skew networks can
result in significant improvement in design performance on Fusion devices.
The nine spines available in a vertical column reside in global networks with two separate regions of
scope: the quadrant global network, which has three spines, and the chip (main) global network, which
has six spines. Note that there are three quadrant spines in each quadrant of the device. There are four
quadrant global network regions per device
The spines are the vertical branches of the global network tree, shown in
spine in a vertical column of a chip (main) global network is further divided into two equal-length spine
segments: one in the top and one in the bottom half of the die.
Each spine and its associated ribs cover a certain area of the Fusion device (the "scope" of the spine;
see
architecture, which defines how a particular spine is driven—either by the signal on the global network
from a CCC, for example, or another net defined by the user
driven from user I/Os on the north and south sides of the die, via analog I/Os configured as direct digital
inputs. The ability to drive spines in the quadrant global networks can have a significant effect on system
performance for high-fanout inputs to a design.
Details of the chip (main) global network spine-selection MUX are presented in
drivers for each spine are located in the middle of the die.
Quadrant spines are driven from a north or south rib. Access to the top and bottom ribs is from the corner
CCC or from the I/Os on the north and south sides of the device. For details on using spines in Fusion
devices, see the Actel application note
Figure 2-13 • Spine-Selection MUX of Global Tree
Figure 2-11 on page
Internal/External
Internal/External
Signal
Signal
2-12). Each spine is accessed by the dedicated global network MUX tree
Global Rib
Using Global Resources in Actel Fusion
Internal/External
Tree Node MUX
(Figure 2-12 on page
R e visio n 1
Signals
Global Driver MUX
Tree Node MUX
Spine
(Figure
2-13).
Internal/External
Tree Node MUX
2-13). Quadrant spines can be
Signals
Figure 2-11 on page
Devices.
Figure
2-13. The spine
2-12. Each