AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 274

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC and Power Characteristics
3- 24
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
Global Clock Dynamic Contribution—P
Sequential Cells Dynamic Contribution—P
Operating Mode, Standby Mode, and Sleep Mode
P
Operating Mode
P
P
Standby Mode
P
Sleep Mode
P
Operating Mode
P
P
Standby Mode
P
Sleep Mode
P
Operating Mode
P
Standby Mode and Sleep Mode
P
Operating Mode
P
TOTAL
STAT
DC8
STAT
STAT
DYN
XTL-OSC
DYN
DYN
CLOCK
CLOCK
S-CELL
P
P
N
N
N
N
N
N
Table 3-16 on page
N
on page
F
N
N
sequential cell is used, it should be accounted for as 1.
) + (N
CLK
STAT
DYN
NVM-BLOCKS
QUADS
INPUTS
OUTPUTS
PLLS
SPINE
ROW
S-CELL
S-CELL
= P
= P
= 0 W
= P
= P
= P
= P
= (P
= 0 W
= N
is the global clock signal frequency.
CLOCK
XTL-OSC
is the total dynamic power consumption.
DC1
DC2
DC3
+ P
is the total static power consumption.
is the number of PLLs available in the device.
is the number of VersaTile rows used in the design—guidelines are provided in
PLLS
STAT
is the number of global spines used in the user design—guidelines are provided in
S-CELL
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
is the number of Analog Quads used in the design.
AC1
3-27.
is the number of I/O input buffers used in the design.
RC-OSC
+ (N
is the number of I/O output buffers used in the design.
* P
+ P
+ P
+ N
is the number of NVM blocks available in the device.
NVM-BLOCKS
DC9
* (P
DYN
S-CELL
SPINE
+ P
)
AC5
3-27.
AB
* P
+ P
+ (
AC2
α
C-CELL
* P
1
TOTAL
/ 2) * P
+ N
DC4
ROW
+ P
) + P
STAT
AC6
NET
R e visio n 1
* PAC3 + N
DC5
DYN
CLOCK
) * F
+ P
+ (N
S-CELL
CLK
INPUTS
QUADS
S-CELL
+ P
* P
OUTPUTS
* P
DC6
AC4
) + (N
) * F
+ P
INPUTS
CLK
MEMORY
* P
DC7
+ P
) + (N
PLL
+ P
OUTPUTS
Table 3-16
NVM
+
*