AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 96

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
Analog Block
2- 80
With the Fusion family, Actel has introduced the world's first mixed-mode FPGA solution. Supporting a
robust analog peripheral mix, Fusion devices will support a wide variety of applications. It is this Analog
Block that separates Fusion from all other FPGA solutions on the market today.
By combining both flash and high-speed CMOS processes in a single chip, these devices offer the best
of both worlds. The high-performance CMOS is used for building RAM resources. These high-
performance structures support device operation up to 350 MHz. Additionally, the advanced Actel
0.13 µm flash process incorporates high-voltage transistors and a high-isolation, triple-well process. Both
of these are suited for the flash-based programmable logic and nonvolatile memory structures.
High-voltage transistors support the integration of analog technology in several ways. They aid in noise
immunity so that the analog portions of the chip can be better isolated from the digital portions,
increasing analog accuracy. Because they support high voltages, Actel flash FPGAs can be connected
directly to high-voltage input signals, eliminating the need for external resistor divider networks, reducing
component count, and increasing accuracy. By supporting higher internal voltages, the Actel advanced
flash process enables high dynamic range on analog circuitry, increasing precision and signal–noise
ratio. Actel flash FPGAs also drive high-voltage outputs, eliminating the need for external level shifters
and drivers.
The unique triple-well process enables the integration of high-performance analog features with
increased noise immunity and better isolation. By increasing the efficiency of analog design, the triple-
well process also enables a smaller overall design size, reducing die size and cost.
The Analog Block consists of the Analog Quad I/O structure, RTC (for details refer to the
Counter System" section on page
single Analog Block macro, with which the user implements this functionality
The Analog Block needs to be reset/reinitialized after the core powers up or the device is programmed.
An external reset/initialize signal, which can come from the internal voltage regulator when it powers up,
must be applied.
2-33), ADC, and ACM. All of these elements are combined in the
R e visio n 1
(Figure
2-65).
"Real-Time