AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 33

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-5 • AFS1500 Global Resource Timing
Table 2-6 • AFS600 Global Resource Timing
Parameter
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a
3. For the derating values at specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a
3. For the derating values at specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKSW
RCKL
RCKH
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
fully loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
fully loaded row (all available flip-flops are connected to the global net in the row).
Commercial Temperature Range Conditions: T
Commercial Temperature Range Conditions: T
Input Low Delay for Global Clock
Input High Delay for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
VersaNet Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are dependent upon I/O standard, and the clock may be
driven and conditioned internally by the CCC module.
page 2-18
delays are measured with minimum and maximum loading, respectively.
Input Low Delay for Global Clock
Input High Delay for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Timing Characteristics
present minimum and maximum global clock delays within the device Minimum and maximum
Description
Description
Min.
1.53
1.53
Min.
1.27
1.26
R e v i s i o n 1
1
1
–2
J
J
–2
= 70°C, Worst-Case VCC = 1.425 V
= 70°C, Worst-Case VCC = 1.425 V
Max.
Max.
1.75
1.79
0.26
1.49
1.54
0.27
Table
2
2
Min.
2-5,
1.74
1.75
Min.
1.44
1.44
Actel Fusion Family of Mixed Signal FPGAs
1
Table
1
–1
–1
Max.
Max.
1.99
2.04
0.29
1.70
1.75
0.31
2-6,
Table 3-7 on page
Table 3-7 on page
2
2
Table
Min.
2.05
2.05
Min.
1.69
1.69
2-7, and
1
1
Std.
Std.
Max.
Max.
2.34
2.40
0.34
2.00
2.06
0.36
Table 2-8 on
3-9.
3-9.
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
2- 17