AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 324

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
5 - 8
Revision
Advance v0.8
(June 2007)
Figure 2-16 • Fusion Clocking Options
to change GND_OSC and VCC_OSC to GNDOSC and VCCOSC.
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
to change the positions of OADIVRST and OADIVHALF, and a note was added.
The
and enabling/disabling the crystal oscillator.
Table 2-11 · Electrical Characteristics of the Crystal Oscillator
change the typical value of I
The
paragraph stating that an external pull-down is required on TRST to power down the
VR.
The
powering down with the VR.
This sentence was updated in the
The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e.,
internal signal or GLC).
In
The method to enable sleep mode was updated for bit 0 in
Control/Status
S2 was changed to D2 in
for RD[31:0] was updated.
The definitions for bits 2 and 3 were updated in
Definition.
Figure 2-46 • FlashROM Timing Diagram
Table 2-26 • FlashROM Access Time
Figure 2-55 • Write Access After Write onto Same
Access After Write onto Same
onto Same Address
Table 2-31 • RAM4K9
The VAREF and SAMPLE functions were updated in
Description.
The title of
add the word "positive."
The
in High Current Drive mode.
The
SAMPLE and BUSY signals and the maximum frequencies for SYSCLK and
ADCCLK.
denominator.
Table 2-46 · Analog Channel Specifications
Direct Input Mode
Table 2-13 • NGMUX Configuration and Selection
"Crystal Oscillator" section
"Gate Driver" section
"1.5 V Voltage Regulator" section
"1.5 V Voltage Regulator" section
"ADC Description" section
EQ 2
Figure 2-72 • Timing Diagram for Current Monitor Strobe
Register.
was updated to add parentheses around the entire expression in the
were updated.
are new.
and
Figure 2-39 • Read Waveform (Pipe Mode, 32-bit access)
Table 2-32 • RAM512X18
was updated to give information about the switching rate
DYNXTAL
Address, and
was updated to include information about controlling
"No-Glitch MUX (NGMUX)" section
was updated to include information about the
for 0.032–0.2 MHz to 0.19.
R e vi s i o n 1
Changes
is new.
and the
was updated.
was updated to add "or floating" in the
was updated to include information on
and
Figure 2-57 • Write Access After Read
"RC Oscillator" section
Table 2-47 · ADC Characteristics in
Table, 10 and 11 were deleted.
were updated.
Address,
Table 2-24 • Page Status Bit
Table 2-36 • Analog Block Pin
Figure 2-56 • Read
Table 2-16 • RTC
was updated to
was updated to
to delete GLA:
were updated
was updated
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2-71,
2-118,
2-68–
2-102
2-121
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