LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 138
![FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-8E-5FTN256C
Manufacturer Part Number
LFXP2-8E-5FTN256C
Description
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256C
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice
Quantity:
63
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Table 9-8. CLKDIVB Port Definition
Table 9-9. CLKDIVB Attribute Definition
CLKDIV Declaration in VHDL Source Code
COMPONENT CLKDIVB
-- synthesis translate_off
-- synthesis translate_on
END COMPONENT;
begin
CLKDIVinst0:
-- synthesis translate_off
-- synthesis translate_on
GENERIC MAP(
GENERIC (
PORT (
attribute GSR : string;
attribute GSR of CLKDIVinst0 : label is “DISABLED”;
PORT MAP(
GSR : in String);
CLKI,RST, RELEASE:IN
CDIV1, CDIV2, CDIV4, CDIV8:OUT
GSR
);
CLKI
RST
RELEASE
CDIV1
CDIV2
CDIV4
CDIV8
);
Name
GSR
CLKI
RST
RELEASE
CDIV1
CDIV2
CDIV4
CDIV8
Name
CLKDIVB
=> “disabled”
=> CLKIsig,
=> RSTsig,
=> RELEASEsig,
=> CDIV1sig,
=> CDIV2sig,
=> CDIV4sig,
=> CDIV8sig
GSR Enable
Description
Clock Input
Reset Input, asynchronously forces all outputs low.
Releases outputs synchronously to input clock.
Divided BY 1 Output
Divided BY 2 Output
Divided BY 4 Output
Divided BY 8 Output
std_logic;
9-16
std_logic);
Description
ENABLED/DISABLED
Value
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
DISABLED
Default
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