LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 174

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-21. FIFO without Output Registers, Start of Data Write Cycle
The WrEn signal must be high to start writing into the FIFO. The Empty and Almost Empty flags are high to begin
and Full and Almost Full are low.
When the first data is written into the FIFO, the Empty flag de-asserts (or goes low), as the FIFO is no longer
empty. In this figure we assume that the Almost Empty setting flag setting is 3 (address location 3). So the Almost
Empty flag gets de-asserted when the third address location is filled.
Now let us assume that we continue to write into the FIFO to fill it. When the FIFO is filled, the Almost Full and Full
Flags are asserted. Figure 10-22 shows the behavior of these flags. In this figure we assume that FIFO depth is 'N'.
Figure 10-22. FIFO without Output Registers, End of Data Write Cycle
In this case, the Almost Full flag is in the 2 location before the FIFO is filled. The Almost Full flag is asserted when
the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO.
Almost Full
Almost
Almost
Almost
Empty
Empty
Reset
Empty
Empty
Clock
WrEn
RdEn
Reset
Clock
WrEn
RdEn
Data
Data
Full
Full
Full
Q
Q
Invalid Data
Data_1
Data_N-2
Data_2
Data_N-1
10-24
Invalid Q
Data_3
Invalid Q
Data_N
Data_4
Data_X
LatticeXP2 Memory Usage Guide
Data_5
Data_X