LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 231

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
IDDRX2B
This module is used when a gearing function is required. This primitive inputs the DDR data at both edges of the
edge clock and generates four streams of data aligned to SCLK. SCLK is always half the frequency of ECLK. It is
recommended that the CLKDIV module or PLL be used to generate the SCLK from the ECLK.
Figure 11-32 shows the primitive symbol for the IDDRX2B mode.
Figure 11-32. IDDRX2B Symbol
Table 11-8 lists the port names and descriptions for the IDDRX2B primitive.
Table 11-8. IDDRX2B Port Names
Figure 11-33 shows the LatticeXP2 Input Register Block configured in the IDDRX2B mode. The DDR registers and
the first set of synchronization registers are clocked by the ECLK input. The SCLK is used to clock the third stage
of register. This primitive will output four streams of data. The 2x gearing function is implemented by using the syn-
chronization registers of the complementary PIO. The clock transfer registers are shared with the output register
block.
D
ECLK
SCLK
CE
RST
QA0, QA1
QB0, QB1
Port Name
I/O
O
O
I
I
I
I
I
DDR data
This clock can be connected to the fast edge clock
This clock should be connected to the FPGA clock
Clock enable signal
Reset to the DDR register
Data at the positive edge of the clock
Data at the negative edge of the clock
ECLK
SCLK
CE
RST
D
IDDRX2B
11-27
QA0
QA1
QB0
QB1
Description
LatticeXP2 High-Speed I/O Interface