LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 146

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Appendix A. Primary Clock Sources and Distribution
Figure 9-22. LatticeXP2 Primary Clock Sources and Distribution
Figure 9-23. LatticeXP2 Primary Clock Muxes
16 PLL outputs
8 CLKDIV outputs
4 PCLK pins
General Routing
CLKDIV
GPLL*
GPLL
PCLKT7
PCLKT6
CLKDIV1
CLKDIV2
CLKDIV4
CLKDIV8
CLKOK2
CLKOK2
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
VCC
General
General
Routing
Routing
2
2
CLK0 CLK1 CLK2 CLK3 CLK4 CLK5
CLK0
36:1 36:1
36:1 36:1
CLK1
QUADRANT BL
QUADRANT TL
CLK2
36:1
36:1
CLK3
36:1 36:1
36:1 36:1
Primary Clocks in Center Switch Box
GPLL* : Available in XP2-17 and larger devices
CLK4
CLK0 - 5
CLK5
36:1
36:1
32:1
32:1
DCS
CLK6
DCS
CLK6
32:1
32:1
32:1
32:1
DCS
DCS
CLK7
CLK7
32:1
32:1
9-24
16 PLL outputs
8 CLKDIV outputs
4 PCLK pins
2 from General
Routing
32:1
32:1
DCS
DCS
CLK7
CLK7
32:1
32:1
32:1
32:1
DCS
DCS
CLK6
CLK6
32:1
32:1
QUADRANT BR
QUADRANT TR
CLK5
CLK5
36:1
36:1
CLK4
CLK4
36:1
36:1
CLK3
CLK3
36:1
36:1
36:1
36:1
CLK2
CLK2
LatticeXP2 sysCLOCK PLL
CLK1
36:1
36:1
CLK1
Design and Usage Guide
36:1
36:1
CLK0
CLK0
General
Routing
General
Routing
3
3
CLKOK2
CLKOK2
CLKDIV1
CLKDIV2
CLKDIV4
CLKDIV8
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
PCLKT2
PCLKT3
CLK6 - 7
CLKDIV
GPLL*
GPLL