LPC1342FBD48,151 NXP Semiconductors, LPC1342FBD48,151 Datasheet - Page 20

• Manufacturer Part Number: LPC1342FBD48,151
• Description: IC MCU 32BIT 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FBD48,151

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: LPC1342
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, USB, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5214

NXP Semiconductors
LPC1311_13_42_43
Product data sheet
7.10.1 Features
7.11.1 Features
7.12 I
7.11 SSP serial I/O controller
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The LPC1311/13/42/43 contain one SSP controller. The SSP controller is capable of
operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
The LPC1311/13/42/43 contain one I
The I
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
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C-bus serial I/O controller
Maximum UART data bit rate of 4.5 MBit/s.
16-byte receive and transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
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C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 August 2010
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C-bus controller.
32-bit ARM Cortex-M3 microcontroller
2
LPC1311/13/42/43
C is a multi-master bus and can be
© NXP B.V. 2010. All rights reserved.
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