LPC1342FBD48,151 NXP Semiconductors, LPC1342FBD48,151 Datasheet - Page 34

IC MCU 32BIT 48LQFP

LPC1342FBD48,151

Manufacturer Part Number
LPC1342FBD48,151
Description
IC MCU 32BIT 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheet

Specifications of LPC1342FBD48,151

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
40
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
LPC1342
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
4 KB
Interface Type
I2C, USB, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-5214

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1342FBD48,151
Manufacturer:
TI
Quantity:
115
Part Number:
LPC1342FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC1311_13_42_43
Product data sheet
9.1 BOD static characteristics
9.2 Power consumption
Table 9.
T
[1]
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC13xx user manual):
Symbol
V
amb
th
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx
user manual.
Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
Configure GPIO pins as outputs using the GPIOnDIR registers.
Write 0 to all GPIOnDATA registers to drive the outputs LOW.
= 25 °C.
Parameter
threshold voltage
BOD static characteristics
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 August 2010
Conditions
interrupt level 0
interrupt level 1
interrupt level 2
interrupt level 3
reset level 0
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
[1]
32-bit ARM Cortex-M3 microcontroller
Min
-
-
-
-
-
-
-
-
-
-
LPC1311/13/42/43
Typ
1.69
1.84
2.29
2.44
2.59
2.74
2.87
2.98
1.49
1.64
© NXP B.V. 2010. All rights reserved.
Max
-
-
-
-
-
-
-
-
-
-
Unit
V
V
V
V
V
V
V
V
V
V
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