ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 143

• Manufacturer Part Number: ML610Q428-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q428-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.2.8
Address: 0F0A4H
Access: R/W
Access size: 8 bits
Initial value: 00H
Address: 0F0A5H
Access: R/W
Access size: 8 bits
Initial value: 00H
PW0CL and PW0CH are special function registers (SFRs) that function as 16-bit binary counters.
When data is written to either PW0CL or PW0CH, PW0CL and PW0CH is set to “0000H”. The data that is written is
meaningless.
When data is read from PW0CL, the value of PW0CH is latched. When reading PW0CH and PW0CL, use a word type
instruction or pre-read PW0CL.
The contents of PW0CH and PW0CL during PWM operation cannot be read depending on the combination of the
PWM clock and system clock. Table 10-1 shows PW0CH and PW0CL read enable/disable for each combination of the
PWM clock and system clock.
PW0DH
At reset
At reset
PW0CL
R/W
R/W
External clock
PWM0 Counter Registers (PW0CH, PW0CL)
PWM clock
HTBCLK
HTBCLK
Table 10-1 PW0CH and PW0CL Read Enable/Disable during PWM0 Operation
LSCLK
LSCLK
P0CK
P0C15
P0C7
R/W
R/W
7
0
7
0
P0C14
P0C6
R/W
R/W
System clock
0
0
6
6
SYSCLK
HSCLK
HSCLK
HSCLK
LSCLK
LSCLK
LSCLK
P0C13
P0C5
R/W
R/W
5
0
5
0
Read enabled
Read enabled. However, to prevent the reading of undefined data
during counting, read consecutively PW0CH or PW0CL twice
until the last data coincides the previous data.
Read disabled
Read enabled
Read disabled
P0C12
P0C4
R/W
R/W
10 – 9
4
0
4
0
PW0CH and PW0CL read enable/disable
P0C11
P0C3
R/W
R/W
3
0
3
0
ML610Q428/ML610Q429 User’s Manual
P0C10
P0C2
R/W
R/W
2
0
2
0
P0C1
P0C9
R/W
R/W
1
0
1
0
Chapter 10 PWM
P0C0
P0C8
R/W
R/W
0
0
0
0