ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 90
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ML610Q428-NNNTBZ03A7
Manufacturer Part Number
ML610Q428-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q428-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
ROHM
Quantity:
750
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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- Download datasheet (3Mb)
• OUTC1, OUTC0 (bits 5, 4)
Note:
− To switch the mode of the high-speed clock generation circuit using the OSCM2, OSCM1 and OSCM0 bits, stop the
− The oscillators that are connected to the P10/OSC0 and P11/OSC1 pins must not exceed 4.2 MHz. In external clock
− When built-in PLL (about 8.192 MHz) oscillation mode is selected (OSCM2 = “0”, OSCM1 = “1”, OSCM0 = “0”),
The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output clock which is output when
the secondary function of the port is used.
OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected.
At system reset, 1/8OSCLK is selected.
high-speed oscillation and set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1
to “0”).
mode, input a clock that does not exceed 4.2 MHz. When a built-in PLL oscillation mode is selected (OSCM2 = “0”,
OSCM1 = “1”, OSCM0 = “0”), 1/2OSCLK (about 4.096 MHz) is output as HSCLK even if OSCLK (SYSC0 = “0”,
SYSC1 = “1”) is selected.
1/2OSCLK (about 4.096 MHz) is output as HSCLK even if OSCLK (SYSC0 = “0”, SYSC1 = “1”) is selected.
OUTC1
0
0
1
1
OUTC0
0
1
0
1
OSCLK
1/2OSCLK
1/4OSCLK
1/8OSCLK (initial value)
6 – 4
Description
ML610Q428/ML610Q429 User’s Manual
Chapter 6 Clock Generation Circuit
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