ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 41
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ML610Q428-NNNTBZ03A7
Manufacturer Part Number
ML610Q428-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q428-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
ROHM
Quantity:
750
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
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3.2
3.2.1
3.2.2
• POR (bit 0)
• XSTR (bit 1)
• WDTR (bit 2)
Address: 0F001H
Access: R/W
Access size: 8 bits
Initial value: Undefined
RSTAT is a special function register (SFR) that indicates the causes by which the reset is generated.
At the occurrence of reset, the contents of RSTAT are not initialized, while the bit indicating the cause of the reset is
set to ”1”. When checking the reset cause using this function, perform write operation to RSTAT in advance and
initialize the contents of RSTAT to “00H”.
[Description of Bits]
Note:
No flag is provided that indicates the occurrence of reset by the RESET_N pin.
Initial value
The POR bit is a flag that indicates that the power-on reset is generated. This bit is set to “1” when powered on.
The XSTR bit is a flag that indicates the generation of low-speed oscillation stop detect reset. When low-speed
oscillation stops for the period specified by the low-speed oscillation stop detection time (TSTOP) or more, this bit is
set to “1”.
The WSDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by
overflow of the watchdog timer is generated.
RSTAT
Address
0F001H
R/W
WDTR
XSTR
POR
Description of Registers
0
1
0
1
0
1
List of Registers
Reset Status Register (RSTAT)
Power-on reset not generated
Power-on reset generated
Low-speed oscillation stop detect reset not occurred
Low-speed oscillation stop detect reset occurred
Watchdog timer reset not occurred
Watchdog timer reset occurred
R/W
―
7
0
Reset status register
Name
R/W
―
0
6
R/W
―
5
0
Symbol (Byte)
Description
Description
Description
R/W
RSTAT
―
4
0
3 – 2
R/W
―
3
0
Symbol (Word)
ML610Q428/ML610Q429 User’s Manual
⎯
WDTR
R/W
2
0
Chapter 3 Reset Function
R/W
R/W
XSTR
R/W
1
x
Size
8
POR
R/W
0
1
Initial value
⎯
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