ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 313
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ML610Q428-NNNTBZ03A7
Manufacturer Part Number
ML610Q428-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q428-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
ROHM
Quantity:
750
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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- Download datasheet (3Mb)
A/D conversion procedure is explained below by taking Figure 23-14 as an example.
RC-ADC interrupt request
CR oscillating
CNTA 2–0
CNTB 2–0
Base clock
(CROS C0)
RADMOD
(bits 4–0)
RADCON
BSCLK
RADINT
(bit 0)
state
HLT
Note) nA0=4B0H, t
Figure 23-14 Timing Diagram for 1 Cycle of A/D Conversion (Example)
0FFFB50H
Stop
000000H
00H
32.768 kHz
SYSCL K
<First Step>
(Counter A reference mode)
=1/32768 Hz;
(Increments by BSCLK)
nA0·t
Oscil lates with RS0
(Increments by
RCCLK (RS0))
BSCLK
01H (ERAD=1)
0.366 sec
=nB0·t
01H
to
RCCLK
: Software processing; (a) to (f): Hardware processing
23 – 18
(RS0)
(b)
(a)
000000H
→ 00000H
Overflow
nB0
(c)
Chapter 23 RC Oscillation Type A/D Converter
INT generated
00H
Stop
ML610Q428/ML610Q429 User’s Manual
(Counter B reference mode)
nB0·tRCCLK(RT0)=nA1·t
1000000H − nB0
Oscillates with RS0
(
(Increments by
RCCLK (RT0))
Increments by BSCLK
01H (ERAD=1)
<Second Step>
12H
)
BSCLK
Overflow
(d)
(e)
(f)
INT generated
nA1
00H
000000H
Stop
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