ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 82
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ML610Q428-NNNTBZ03A7
Manufacturer Part Number
ML610Q428-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q428-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
ROHM
Quantity:
750
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
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- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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- Download datasheet (3Mb)
5.3.4
Notes are different in programming depending on whether a subroutine is called or not by the program in executing an
interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or
non-maskable.
State A: Maskable interrupt is being processed
A-1: When a subroutine is not called by the program in executing an interrupt routine
Example of description: State A-1-1
Intrpt_A-1-1;
A-1-1: When multiple interrupts are disabled
A-1-2: When multiple interrupts are enabled
DI
RTI
:
:
:
• Processing immediately after the start of interrupt routine execution
• Processing at the end of interrupt routine execution
• Processing immediately after the start of interrupt routine execution
• Processing at the end of interrupt routine execution
No specific notes.
Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register
to PSW.
Specify “PUSH ELR, EPSW” to save the interrupt return address and the PSW status in the stack.
Specify “POP PC, PSW” instead of the RTI instruction to return the contents of the stack to PC and PSW.
Notes on Interrupt Routine
; A-1-1 state
; Disable interrupt
; Return PC from ELR
; Return PSW form EPSW
; End
5 – 23
Example of description: State A-1-2
Intrpt_A-1-2;
PUSH ELR, EPSW
EI
POP PC, PSW
:
:
:
:
:
ML610Q428/ML610Q429 User’s Manual
Chapter 5 Interrupts (INTs)
; Start
; Save ELR and EPSW at the
; Enable interrupt
; Return PC from the stack
; Return PSW from the stack
; End
beginning
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