ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 363

• Manufacturer Part Number: ML610Q428-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q428-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.3.3
When the programmable display allocation function is used (DASN bit of DSPMOD1 register is “1”), display registers
(DSPR00 to FE) segment mapping can be set in bit units according to the contents of display allocation registers A and B
(DSmCnA, DSmCnB: m = 0 to 63, n = 0 to 7).
Table 24-7 shows the frame frequencies and the duty conditions that allow the use of the programmable allocation
function.
Note:
- When the duty is other than those indicated in Table 24-7, the programmable allocation function can not be used
regardless of the content of the DASN bit of DSPMOD1. The programmable display allocation function is available only
when 1/1~1/8 duty is selected (when using eight COMs or less for display), it does not work when 1/9~1/24 duty is
selected (when using nine COMs or more for display).
- Select type 3 for the display register segment map (Set DADM1 bit of DSPMOD1 register to “1”) when using the
programmable allocation function.
Figure 24-8 shows the configuration when using the programmable display allocation function.
0F5FEH
0F5FFH
0F402H
0F401H
0F400H
Figure 24-8 Configuration When Using the Programmable Display Allocation Function
Display allocation register A
Data bus
Segment Mapping When the Programmable Display Allocation Function is Used
Table 24-7 Conditions That Allow the Use of Programmable Allocation Function
DS63C7A
DS62C7A
DS2C0A
DS1C0A
DS0C0A
8
Specifies the
addresses of a
display register
Frame frequency
Approx. 102 Hz
Approx. 64 Hz
Approx. 73 Hz
Approx. 85 Hz
Mapping specification of SEG63-COM7
Mapping specification of SEG62-COM7
Mapping specification of SEG2-COM0
Mapping specification of SEG1-COM0
Mapping specification of SEG0-COM0
Display register
DSPRFE
DSPR00
|
Duty that allows the use of duty
24 – 45
8
Display allocation register B
1/1 to 1/8 Duty
1/1 to 1/7 Duty
1/1 to 1/6 Duty
1/1 to 1/5 Duty
DS63C7B
DS62C7B
DS2C0B
DS1C0B
DS0C0B
Selector
3
ML610Q428/ML610Q429 User’s Manual
Specifies a bit of
a display register
0F7FFH
0F7FEH
0F602H
0F601H
0F600H
1
Chapter 24 LCD Drivers
Segment
drivers
SEG63
SEG62
SEG2
SEG1
SEG0