ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 152

• Manufacturer Part Number: ML610Q429-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q429-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3 Description of Operation
The PWMn(n=0 to 2) counter registers (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the
first falling edge of the PWMn clock (PnCK) that are selected by the PWMn control register 0 (PWnCON0) when the
PnRUN bit of PWMn control register 1 (PWnCON1) is set to “1” and increment the count value on the 2nd falling
edge.
When the count value of PWMn counter registers and the value of the PWMn duty buffer (PWnDBUF) coincide, the
PWMn flag (PnFLG) is set to “0” on the next timer clock falling edge of PnCK.
When the count value of PWMn counter registers and the value of the PWMn period buffer (PWnPBUF) coincide, the
PWMn flag (PnFLG) is set to “1” on the next falling edge of PnCK and PWMn counter registers is set to “0000H” and
incremental counting continues. At the same time, the value of the PWMn duty register (PWnDH, PWnDL) is
transferred to the PWMn duty buffer (PWnDBUF) and the value of PWMn period register (PWnPH, PWnPL) to the
PWMn period buffer (PWnPBUF).
When the PnRUN bit is set to “0”, PWMn counter registers stop counting after counting once the falling of the PWMn
clock (PnCK). Confirm that PWnCH and PWnCL are stopped by checking that the PnSTAT bit of the PWMn control
register 1 (PWnCON1) is “0”. When the PnRUN bit is set to “1” again, PWMn counter registers restarts incremental
counting from the previous value on the falling edge of PnCK.
To initialize PWMn counter registers to “0000H”, perform write operation in either of PWnCH or PWnCL. At that
time, PnFLG is also set to “1”. When data is written in the PWMn duty register (PWnDH, PWnDL) during count stop
(PnRUN is in a “1” state), the data is transferred to the PWMn duty buffer (PWnDBUF) and when data is written in the
PWMn period register (PWnPH, PWnPL), the data is transferred to the PWMn period buffer (PWnPBUF).
The PWMn clock, the point at which an interrupt of PWMn occurs, and the logic of the PWMn output are selected by
PWMn control register 0 (PWnCN0).
The period of the PWMn signal (TPWPn) and the first half duration (TPWDn) of the duty are expressed by the
following equations.
T
T
PWnP:
PWnD:
PnCK:
PWPn
PWPn
=
=
PWMn period registers (PWnPH, PWnPL) setting value (0001H to 0FFFFH)
PWMn duty registers (PWnDH, PWnDL) setting value (0000H to 0FFFEH)
Clock frequency selected by the PWMn control register 0 (PWnCON0)
PnCK (Hz)
PnCK (Hz)
PWnP + 1
PWnD + 1
(n = 0 to 2)
10 – 18
ML610Q428/ML610Q429 User’s Manual
Chapter 10 PWM