ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 96

• Manufacturer Part Number: ML610Q429-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q429-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.2.3
6.3.2.4
The PLL oscillation circuit generates a clock of 8.192 MHz (= 32.768 kHz × 250) ±2.5%. When the PLL oscillation
clock (OSCLK) reaches within 8.192 MHz±2.5%, the LPLL flag of FCON1 is set.
In built-in PLL oscillation mode (OSCM2 = “0”, OSCM0 = “0”, OSCM1 = “1”), supply of OSCLK (high-speed
oscillation clock) is started when PLL oscillation clock pulse count reaches 4096 after oscillation is enabled (ENOSC is
set to “1”).
In PLL oscillation mode, both the P10/OSC0 pin and the P11/OSC1 pin can be used as general-purpose input ports.
Figure 6-6 shows the circuit configuration in PLL oscillation mode.
Note:
The PLL oscillation mode can be used within a V
operating voltage range by using the power supply voltage detection circuit (BLD).
When OSCLK is selected through SYSC1 or SYSC0 of FCON0 in PLL oscillation mode, about 4.096MHz, which is
the same as 1/2OSCLK, is selected.
To use a PLL oscillation mode, a frequency of low-speed crystal oscillation 32.768kHz is necessary. The frequency of
32.768kHz is not adjusted by the frequency adjustment circuit of the time base counter.
In external clock input mode, external clock is input from the P10/OSC0 pin. The P11/OSC1 pin can be used as a
general-purpose input port.
Figure 6-7 shows the circuit configuration in external clock input mode.
Notes:
− The external clock input mode can be used within a V
− Since the diodes are included between the P10/OSC0 pin and V
− If the P10/OSC0 pin is left open in external clock input mode, excessive current can flow. Therefore, make sure that
− The clock that is input should not exceed the guaranteed maximum operating frequency 4.2 MHz of the system
the operation voltage range by using the power supply voltage detection circuit (BLD).
apply voltages higher than V
the “H” level (V
clock (SYSCLK) of this LSI.
External clock input
Built-in PLL Oscillation Mode
External Clock Input Mode
32.768 kHz
DD
) or the “L” level (V
Figure 6-7 Circuit Configuration in External Clock Input Mode
Figure 6-6 Circuit Configuration in PLL Oscillation Mode
DD
and lower than V
P10/OSC0
PLL oscillation
SS
circuit
V
) is input.
DDL
V
DD
SS
DD
to the P10/OSC0 pin.
range of 1.8 V to 3.6 V. Select a frequency according to the
6 – 10
DD
range of 1.8 V to 3.6 V. Select a frequency according to
STOP mode
ENOSC (Enables oscillation)
Count: 4096
DD
and between the P10/OSC0 pin and V
ML610Q428/ML610Q429 User’s Manual
Chapter 6 Clock Generation Circuit
STOP mode
ENOSC (Enables oscillation)
High-speed oscillation clock
(OSCLK)
OSCLK
(High-speed oscillation clock)
SS
, do not