ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 334
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ML610Q429-NNNTBZ03A7
Manufacturer Part Number
ML610Q429-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q429-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm
Quantity:
900
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
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- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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- Download datasheet (3Mb)
24.2.7
• a7-a0 (bits 7-0)
Address: 0F400H to 0F5FFH
Access: R/W
Access size: 8 bits
Initial value: Undefined
DSmCnA (m= 0 to 63, n = 0 to 7) are special function registers (SFRs) that are used for the programmable display
allocation function.
Each valid bit of DSmCnA becomes undefined at system reset.
When the programmable display allocation function is not used (DASN bit of DSPMOD1 reigster is reset to “0”),
DSmCnA can be used as data memory space (512-byte RAM).
Table 24-2 shows a list of the display allocation register A.
[Description of Bits]
Initial value
DSmCnA
The a7 to a0 bits of DSmCnA (m= 0 to 63, n = 0 to 7) are used to select the lower 8 bits of the addresses of the display
registers (DSPR00 to FE) that are output to common n of segment m.
Set DSmCnA when the DASN bit of the display mode register 1 (DSPMOD1) is “0”.
When the DASN bit is “1”, access from the CPU is invalid.
R/W
Display Allocation Register A (DS0C0A to DS63C7A)
R/W
a7
7
x
R/W
a6
6
x
R/W
a5
5
x
R/W
a4
4
x
24 – 16
R/W
a3
3
x
ML610Q428/ML610Q429 User’s Manual
R/W
a2
2
x
R/W
Chapter 24 LCD Drivers
a1
1
x
R/W
a0
0
x
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