ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 57
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ML610Q429-NNNTBZ03A7
Manufacturer Part Number
ML610Q429-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q429-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
ML610Q429-NNNTBZ03A7
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Quantity:
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Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
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Quantity:
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4.3.3.3
• If the ELEVEL bit is 0H, it indicates that the CPU is performing neither nonmaskable interrupt processing nor
• If the ELEVEL bit is 1H, it indicates that the CPU is performing maskable interrupt processing or software interrupt
• If the ELEVEL bit is 2H, it indicates that the CPU is performing non-maskable interrupt processing. (ELEVEL is set
• If the ELEVEL bit is 3H, it indicates that the CPU is performing interrupt processing specific to the emulator. This
The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of
the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to
IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.
For details of PSW and the IE and IRQ registers, see “nX-U8/100 Core Instruction Manual” and Chapter 5, “Interrupt”,
respectively.
Table 4-1 and Table 4-2 show the return operations from STOP/HALT mode.
Notes:
maskable interrupt processing nor software interrupt processing.
processing. (ELEVEL is set during interrupt transition cycle.)
during interrupt transition cycle.)
setting is not allowed in normal applications.
ELEVEL
ELEVEL
0, 1, 2
0, 1
2,3
3
*
*
*
*
Note on Return Operation from STOP/HALT Mode
Table 4-1 Return Operation from STOP/HALT Mode (Non-Maskable Interrupt)
Table 4-2 Return Operation from STOP/HALT Mode (Maskable Interrupt)
MIE
MIE
0
1
1
*
*
*
*
*
IEn.m
IEn.m
0
1
1
1
−
−
−
*
IRQn.m
IRQn.m
0
1
1
0
1
1
1
1
Not returned from STOP/HALT mode.
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. The program operation does not go to the
interrupt routine.
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
Not returned from STOP/HALT mode.
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. The program operation does not go to the
interrupt routine.
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
4 – 14
Return operation from STOP/HALT mode
Return operation from STOP/HALT mode
ML610Q428/ML610Q429 User’s Manual
Chapter 4 MCU Control Function
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