ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 47

• Manufacturer Part Number: ML610Q429-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q429-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.2.3 Standby Control Register (SBYCON)
• STP (bit 1)
• HLT (bit 0)
Address: 0F009H
Access: W
Access size: 8 bits
Initial value: 00H
SBYCON is a special function register (SFR) to control operating mode of MCU.
[Description of Bits]
Note:
The mode can not be changed to HALT mode or STOP mode on the condition of that both any interrupt enable flag
and the corresponding interrupt request flag are “1”(An interrupt request occurrence with resetting MIE flag will have
the condition).
When a maskable interrupt source (interrupt with enable bit) occurs while the MIE flag of the program status word
(PSW) in the nX-U8/100 core is “0”, the STOP mode and the HALT mode are simply released and interrupt processing
is not performed. Refer to the “nX-U8/100 Core Instruction Manual” for details of PSW.
Initial value
SBYCON
The STP bit is used for setting the STOP mode. When the STP bit is set to “1” with the stop code adapter enabled by
using STPACP, the mode is changed to the STOP mode. When the NMI interrupt request or the P00–P03 interrupt
request enabled by the interrupt enable register 1 (IE1) is issued, the STP bit is set to “0” and the LSI returns to the
program run mode.
The HALT bit is used for setting a HALT mode. When the HALT bit is set to “1”, the mode is changed to the HALT
mode. When the NMI interrupt request, WDT interrupt request, or enabled (the interrupt enable flag is “1”) interrupt
request is issued, the HALT bit is set to “1” and the mode is returned to program run mode.
W
STP
0
0
1
1
―
W
HLT
7
0
0
1
0
1
Program run mode (initial value)
HALT mode
STOP mode
Prohibited
―
W
6
0
―
W
5
0
―
W
4
0
4 – 4
Description
―
W
3
0
ML610Q428/ML610Q429 User’s Manual
Chapter 4 MCU Control Function
―
W
2
0
STP
W
1
0
HLT
W
0
0