LM97593VH National Semiconductor, LM97593VH Datasheet - Page 26

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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reference voltage, V
each other and be centered around V
1.3.1 Single-Ended Operation
Performance with differential input signals is better than with
single-ended signals. For this reason, single-ended operation
is not recommended. However, if single ended-operation is
required and the resulting performance degradation is ac-
ceptable, one of the analog inputs should be connected to the
d.c. mid point voltage of the driven input. The peak-to-peak
input signal at the driven input pin should be twice the refer-
ence voltage to maximize SNR and SINAD performance
(Figure 17b). For example, set V
and drive V
Because very large input signal swings can degrade distortion
performance, better performance with a single-ended input
can be obtained by reducing the reference voltage when
maintaining a full-range output.
1.3.2 Driving the Analog Inputs
The V
switch followed by a switched-capacitor amplifier. As the in-
ternal sampling switch opens and closes, current pulses oc-
cur at the analog input pins, resulting in voltage spikes at the
signal input pins. As the driving source attempts to counteract
these voltage spikes, it may add noise to the signal at the ADC
analog input. C1, C2, and C3 as shown in Figure 45 improve
the ADC performance by filtering these voltage spikes. These
components should be placed close to the ADC inputs be-
cause the input pins of the ADC are the most sensitive part of
the system and this is the last opportunity to filter that input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. For wide-
band undersampling applications, the RC pole should be set
at about 1.5 to 2 times the maximum input frequency to main-
tain a linear delay response. The values of the RC shown in
Figure 45 are suitable for applications with input frequencies
up to approximately 70MHz.
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
of 1.0V to 2.0V and be a value such that the peak excursions
of the analog signal do not go more negative than ground or
more positive than 2.6V. See Section 1.2.
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CK, REFSEL/
DCS.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in the
range of 10 MHz to 65 MHz. The higher the input frequency,
the more critical it is to have a low jitter clock. The trace car-
rying the clock signal should be as short as possible and
should not cross any other signal line, analog or digital, not
even at 90°.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency too low, the charge on
internal capacitors can dissipate to the point where the accu-
racy of the output data will degrade. This is what limits the
lowest sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
IN
+ and the V
IN
+ with a signal range of 0.5V to 2.5V.
IN
− inputs of the ADC consist of an analog
REF
, be 180 degrees out of phase with
REF
CM
to 1.0V, bias V
CM
, should be in the range
.
IN
− to 1.5V
26
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance.
It is highly desirable that the the source driving the ADC
CLK pin only drive that pin. However, if that source is used to
drive other things, each driven pin should be a.c. terminated
with a series RC to ground such that the resistor value is equal
to the characteristic impedance of the clock line and the ca-
pacitor value is
where t
"L" is the line length and Z
of the clock line. This termination should be as close as pos-
sible to the ADC clock pin but beyond it as seen from the clock
source. Typical t
board material. The units of "L" and t
(inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the LM97593 has a Duty Cycle Stabilizer which can
be enabled using the REFSEL/DCS pin. It is designed to
maintain performance over a clock duty cycle range of 30%
to 70% at 65 MSPS.
2.2 REFSEL/DCS
This pin is used in conjunction with V
reference source and turn the Duty Cycle Stabilizer (DCS) on
or off.
When REFSEL/DCS is LOW and V
1.0V reference is selected and DCS is On.
When REFSEL/DCS is HIGH, an external reference voltage
in the range of 0.8V to 1.2V should be applied to the VREF
input. DCS is On.
With REFSEL/DCS pin connected to V
internal 1.0V reference is selected and DCS is Off.
When enabled, duty cycle stabilization can compensate for
clock inputs with duty cycles ranging from 30% to 70% and
generate a stable internal clock, improving the performance
of the part.
2.3 PD
The PD pin, when high, holds the ADC in a power-down mode
to conserve power when the converter is not being used. The
output data pins are undefined and the data in the pipeline is
corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on pins 15, 16, 17, 22, 23 and 24.
These capacitors lose their charge in the Power Down mode
and must be recharged by on-chip circuitry before conver-
sions can be accurate. Smaller capacitor values allow slightly
faster recovery from the power down mode, but can result in
a reduction in SNR, SINAD and ENOB performance.
REFSEL/
DCS (pin 8)
Logic Low
Logic High
V
V
V
V
COM
COM
COM
COM
A or
B
A or
B
TABLE 1. V
PD
is the signal propagation time down the clock line,
V
Logic High
0.8 to 1.2V
Logic High
0.8 to 1.2V
PD
REF
REF
is about 150 ps/inch (60 ps/cm) on FR-4
(pin 21) Reference
, REFSEL/DCS Pin Functions
O
is the characteristic impedance
Internal 1.0 V ON
External
Internal 1.0V OFF
External
REF
REF
PD
is HIGH, the internal
COM
(pin 21) to select the
should be the same
A or V
DCS
ON
OFF
COM
(Eq. 4)
B, the