LM97593VH National Semiconductor, LM97593VH Datasheet - Page 4

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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Pin No.
99
81
84, 86:88, 90,
91, 93:97,
104:106, 108,
109
112:114
111
77
37
46
62, 63, 69:73,
75
48, 50, 52:57 A[7:0]
59
Symbol
SCK_IN
SFS
POUT[15:0]
POUT_SEL[2:0]
POUT_EN
RDY
CK
SI
D[7:0]
RD
Equivalent Circuit
Input
Output
Output
Input
Input
Output
Input
Input
Input/Output
Input
Input
Description
SERIAL DATA CLOCK INPUT, Active high or low
Data bits from a serial daisy-chain slave are clocked into a serial daisy-
chain master on the falling edge of SCK_IN (rising if SCK_POL=1 on
the slave). Tie low if not used.
SERIAL FRAME STROBE, Active high or low
The serial word strobe. This strobe delineates the words within the serial
output streams. This strobe is a pulse at the beginning of each serial
word (PACKED=0) or each serial word I/Q pair (PACKED=1). The
polarity of this signal is user programmable. This pin is tri-stated at power
up and is enabled by the SOUT_EN control register bit. See and timing
diagrams. In Debug Mode SFS=DEBUG[2].
PARALLEL OUTPUT DATA, Active high
The output data is transmitted on these pins in parallel format. The
POUT_SEL[2:0] pins select one of eight 16-bit output words. The
POUT_EN pin enables these outputs. POUT[15] is the MSB. In Debug
Mode POUT[15:0]=DEBUG[19:4].
PARALLEL OUTPUT DATA SELECT, Active high
The 16-bit output word is selected with these 3 pins according to . Not
used in Debug Mode. For a serial daisy-chain master, POUT_SEL
[2:0] become inputs from the slave: POUT_SEL[2]=SFS
POUT_SEL[1]=BOUT
not used.
PARALLEL OUTPUT ENABLE. Active low
This pin enables the chip to output the selected output word on the
POUT[15:0] pins. Not used in Debug Mode. Tie high if not used.
READY FLAG, Active high or low
The chip asserts this signal to identify the beginning of an output sample
period (OSP). The polarity of this signal is user programmable. This
signal is typically used as an interrupt to a DSP chip, but can also be
used as a start pulse to dedicated circuitry. This pin is active regardless
of the state of SOUT_EN. In Debug Mode RDY=DEBUG[3].
INPUT CLOCK. Active high
The clock input to the chip. The The V
are sampled on the rising edge of this signal. SI is clocked into the chip
on the rising edge of CK.
SYNC IN. Active low
The sync input to the chip. The decimation counters, dither, and NCO
phase can be synchronized by SI. This sync is clocked into the chip on
the rising edge of CK. Tie this pin high if external sync is not required.
All sample data is flushed by SI. To properly initialize the DVGA
ASTROBE and BSTROBE are asserted during SI.
DATA BUS. Active high
This is the 8 bit control data I/O bus. Control register data is loaded into
the chip or read from the chip through these pins. The chip will only drive
output data on these pins when CE is low, RD is low, and WR is high.
ADDRESS BUS. Active high
These pins are used to address the control registers within the chip.
Each of the control registers within the chip are assigned a unique
address. A control register can be written to or read from by setting A
[7:0] to the register’s address and setting CE, RD, and WR
appropriately.
READ ENABLE. Active low
This pin enables the chip to output the contents of the selected register
on the D[7:0] pins when CE is also low.
4
SLAVE
, and POUT_SEL[0]=AOUT
IN
A and V
IN
B analog input signals
SLAVE
SLAVE
. Tie low if
,