LM97593VH National Semiconductor, LM97593VH Datasheet - Page 32

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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decreases relative to the output sample rate, the CIC droop
compensation performed by F1 may no longer be required.
4.7 Overall Channel Gain
The overall gain of the chip is a function of the amount of
decimation (N), the settings of the “SHIFT UP” circuit
(SCALE), the GAIN setting, the sum of the F1 coefficients,
and the sum of the F2 coefficients. The overall gain is shown
below in Equation 2.
Where:
and:
It is assumed that the DDC output words are treated as frac-
tional 2’s complement words. The numerators of G
G
F1 and F2, respectively. For the STD and GSM sets, G
G
in (Eq. 6) is cancelled by the DVGA operation so that the en-
tire gain of the DRCS is independent of the DVGA setting
when EXP_INH=0. The 1/2 appearing in (Eq. 6) is the result
of the 6dB conversion loss in the mixer. For full-scale square
F2
F2
FIGURE 32. CIC, F1, & F2 GSM Passband Flatness
equal the sums of the impulse response coefficients of
are nearly equal to unity. Observe that the AGAIN term
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(Eq. 6)
(Eq. 7)
(Eq. 8)
F1
F1
and
and
32
wave inputs the 1/2 should be set to 1 to prevent signal dis-
tortion.
4.8 Data Latency and Group Delay
The LM97593 latency calculation assumes that the FIR filter
latency will be equal to the time required for data to propagate
through one half of the taps. The CIC filter provides 4N equiv-
alent taps where N is the CIC decimation ratio. F1 and F2
provide 21 and 63 taps respectively. When these filters are
reflected back to the input rate, the effective taps are in-
creased by decimation. This results in a total of 151N taps.
The total latency is found by dividing the number of taps by 2
and adding pipeline delays. When the F2 decimation is 2 the
latency is 80N. When the F2 decimation is 4 the latency is
82N. The LM97593 filters are linear phase filters so the group
delay remains constant.
5.0 OUTPUT MODES
After processing by the DDC, the data is then formatted for
output.
All output data is two’s complement. The serial outputs
power up in a tri-state condition and must be enabled
when the chip is configured. Parallel outputs are enabled
by the POUT_EN pin.
Output formats include truncation to 8 or 32 bits, rounding to
16 or 24 bits, and a 12-bit floating point format (4-bit exponent,
8-bit mantissa, 138dB numeric range). This function is per-
formed in the OUTPUT CIRCUIT shown in Figure 33.
The channel outputs are accessible through serial output pins
and a 16-bit parallel output port. The RDY pin is provided to
notify the user that a new output sample period (OSP) has
begun. OSP refers to the interval between output samples at
the decimated output rate. For example, if the input rate (and
clock rate) is 52 MHz and the overall decimation factor is 192
(N=48, F2 decimation=2) the OSP will be 3.69 microseconds
which corresponds to an output sample
FIGURE 33. LM97593 output circuit
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