LM97593VH National Semiconductor, LM97593VH Datasheet - Page 38

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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AGC_IC_B
AGC_RB_A
AGC_RB_B
TEST_REG
Reserved
Reserved
DEBUG_EN
DEBUG_TAP
DITH_A
DITH_B
AGC_TABLE
F1_COEFF
F2_COEFF
Register Name
Register Name
Width
Width
32B
22B
64B
14b
1B
1B
1B
1B
1B
1b
5b
1b
1b
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
-
-
Default
Default
0
0
0
0
0
0
1
1
0
0
0
-
-
a
a
28(MSBs)
27(LSBs)
128-159
160-181
182-245
Addr
Addr
24
25
26
29
30
31
31
31
31
Bit
7:0
7:0
7:0
7:0
5:0
7:0
Bit
7:0
5:1
7:0
7:0
7:0
0
6
7
38
AGC fixed gain for channel B. Format is an 8-bit, unsigned
magnitude number. The channel B DVGA gain will be set to the
inverted three MSBs.
AGC integrator readback value for channel A. Format is an 8-
bit, unsigned magnitude number. The user can read the
magnitude MSBs of the channel A integrator from this register.
AGC integrator readback value for channel B. Format is an 8-
bit, unsigned magnitude number. The user can read the
magnitude MSBs of the channel B integrator from this register.
Test input source. Instead of processing values from the
A|BIN pins, the value from this location is used instead. Format
is 14-bit 2s complement number spread across 2 registers.
For future use.
For future use
0=Normal. 1=Enables access to the internal probe points.
Selects internal node tap for debug.
0 selects F1 output for BI, 20 bits
1 selects F1 output for BQ, 20 bits
2 selects F1 output for AQ, 20 bits
3 selects F1 output for AI, 20 bits
4 selects F1 input for BI, 20 bits
5 selects F1 input for BQ, 20 bits
6 selects F1 input for AI, 20 bits
7 selects F1 input for AQ, 20 bits
8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0.
9 selects NCO A, sine output, 17 bits, 3 LSBs are 0.
10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0.
11 selects NCO B, sine output, 17 bits, 3 LSBs are 0.
12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0.
13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0.
14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0.
15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0.
16 selects AGC CIC filter output. 9 MSBs from ch A, next 9 bits
from ch B, 2 LSBs are 0.
17-31 Reserved.
0=Disable NCO dither source for channel A. 1=Enable.
0=Disable NCO dither source for channel B. 1=Enable.
RAM space that defines key AGC loop parameters. Format is
32 separate 8-bit, 2’s complement numbers. This is common to
both channels.
Coefficients for F1. Format is 11 separate 16-bit, 2’s
complement numbers, each one spread across 2 registers. The
LSBs are in the lower registers. For example, coefficient h0[7:0]
is in address 160, h0[15:8] is in address 161, h1[7:0] is in
address 162, h1[15:8] is in address 163. PAGE_SEL_F1=1
maps these addresses to coefficient memory B.
Coefficients for F2. Format is 32 separate 16-bit, 2’s
complement numbers, each one spread across 2 registers. The
LSBs are in the lower registers. For example, coefficient h0[7:0]
is in address 182, h0[15:8] is in address 183, h1[7:0] is in
address 184, h1[15:8] is in address 185. PAGE_SEL_F2=1
maps these addresses to coefficient memory B.
Description
Description