LM97593VH National Semiconductor, LM97593VH Datasheet - Page 28

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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the compensation is dependent on timing and the accuracy
of the DVGA gain step. The LM97593 allows the timing of the
gain compensation to be adjusted in the EXT_DELAY regis-
ter; see the end of section 6.0 AGC for more information. The
AGC requires 21 bits (14-bit internal bus output + 7-bit shift)
to represent the full linear dynamic range of the signal. The
output word must be set to either 24-bit or 32-bit to take ad-
vantage of the entire dynamic range available. The LM97593
can also be configured to output a floating point format with
up to 138dB of numerical resolution using only 12 output bits.
The “SHIFT UP” circuit will be discussed in the section 4.2
Four Stage CIC Filter.
A 4-stage cascaded-integrator-comb (CIC) filter and a two-
stage decimate by 4 or 8 finite impulse response (FIR) filter
are used to lowpass filter and isolate the desired signal. The
CIC filter reduces the sample rate by a programmable factor
ranging from 8 to 2048 (decimation ratio). The CIC outputs
are followed by a gain stage and then followed by a two-stage
decimate by 4 or 8 filter. The gain circuit allows the user to
boost the gain of weak signals by up to 42 dB in 6 dB steps.
It also rounds the signal to 21 bits and saturates at plus or
minus full scale.
The first stage of the two stage filter is a 21-tap, symmetric
decimate by 2 FIR filter (F1) with programmable 16 bit tap
weights. The coefficients of the first 11 taps are downloaded
to the chip as 16 bit words. Since the filter is a symmetric
configuration only the first 11 coefficients must be loaded.
Section 4.4 First Programmable FIR Filter provides a generic
set of coefficients that compensate for the rolloff of the CIC
filter and provide a passband flat to 0.01dB with 70 dB of out
of band rejection. A second coefficient set is provided that has
a narrower output passband and greater out-of-band rejec-
tion. The second set of coefficients is ideal for systems such
as GSM where far-image rejection is more important than ad-
jacent channel rejection.
The second stage is a 63 tap decimate by 2 or 4 pro-
grammable FIR filter (F2) also with 16 bit tap weights. Filter
coefficients for a flat response from -0.4FS to +0.4FS of the
output sample rate with 80dB of out of band rejection are pro-
vided in Section 4.5 Second Programmable FIR Filter. A
second set of F2 coefficients is also provided to enhance per-
FIGURE 20. Example of NCO spurs due to phase
Complex NCO Output Phase Dither Disabled
(Before Phase Dithering)
truncation
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28
formance for GSM systems. The user can also design and
download their own final filter to customize the channel’s
spectral response. Typical uses of programmable filter F2 in-
clude matched (root-raised cosine) filtering, or filtering to
generate oversampled outputs with greater out of band re-
jection. The 63 tap symmetrical filter is downloaded into the
chip as 32 words, 16 bits each. Saturation to plus or minus
full scale is performed at the output of F1 and F2 to clip the
signal rather than allow it to roll over.
The LM97593 provides two sets of coefficient memory for
both F1 and F2. These coefficient memories can be indepen-
dently routed to channel A, channel B, or both channel A and
B with a crossbar switch. The coefficients can be switched on
the fly but some time will be required before valid output data
is available.
4.1 The Numerically Controlled Oscillator
The tuning frequency of each down converter is specified as
a 32 bit word (.02Hz resolution at CK=52MHz) and the phase
offset is specified as a 16 bit word (.005
eters are applied to the Numerically Controlled Oscillator
(NCO) circuit to generate sine and cosine signals used by the
digital mixer. The NCOs can be synchronized with NCOs on
other chips via the sync pin SI. This allows multiple down
converter outputs to be coherently combined, each with a
unique phase and amplitude.
The tuning frequency is set by loading the FREQ register ac-
cording to the formula FREQ = 2
desired tuning frequency and F
FREQ is a 2’s complement word. The range for F is from
-FCK/2 to +FCK(1-2
If a sub-sampled signal is in an even Nyquist zone the sam-
pling process causes the order of the I and Q components to
be reversed. Should this occur simply invert the polarity of the
tuning frequency F.
The 2’s complement format represents full-scale negative as
10000000 and full-scale positive as 01111111 for an 8-bit ex-
ample.
The 16 bit phase offset is set by loading the PHASE register
according to the formula PHASE = 2
desired phase in radians ranging between 0 and 2
FIGURE 21. Example of NCO spurs due to phase
Complex NCO Output Phase Dither Enabled
(After Phase Dithering)
-31
)/2.
truncation
CK
32
is the chip’s clock rate.
16
F/F
P/2
o
). These two param-
CK
π
, where F is the
, where P is the
π
30008799
. PHASE