DSPIC30F2010-30I/SPG Microchip Technology, DSPIC30F2010-30I/SPG Datasheet - Page 24

• Manufacturer Part Number: DSPIC30F2010-30I/SPG
• Description: 16BIT 30MIPS DSPIC, 30F2010, DIP28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F2010-30I/SPG

• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F
6.
FIGURE 2-7:
7.
FIGURE 2-8:
8.
DS70082E-page 22
1. PUSH DOEND
2. DO LABEL,#COUNT
2a.Second Word
3. 1st Instruction of Loop
1. MOV.b W0,[W1]
2. MOV.b [W1],PORTB
2a.Stall (NOP)
3. MOV.b W0,PORTB
Two-word instructions for DO. In these instruc-
tions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require 2 cycles, as shown in
Figure 2-7.
Instructions that are subjected to a stall due to a
data dependency between the X RAGU and X
WAGU. An additional cycle is inserted to resolve
the resource conflict, as shown in Figure 2-8.
Instruction stalls caused by data dependencies
are further discussed in Section 4.0.
Interrupt
Section 5.0 for details on interrupts.
recognition
INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW
INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
Fetch 1
T
Fetch 1
execution.
CY
T
0
CY
0
Execute 1
Fetch 2L
T
Execute 1
Fetch 2
Refer
CY
Advance Information
T
1
CY
1
to
NOP
Fetch 2H
T
NOP
Stall
CY
T
2
CY
2
Execute 2
Execute 2
Fetch 3
T
Fetch 3
CY
T
3
CY
3
Execute 3
T
Execute 3
CY
4
T
 2004 Microchip Technology Inc.
CY
4
T
CY
5