DSPIC30F2010-30I/SPG Microchip Technology, DSPIC30F2010-30I/SPG Datasheet - Page 97
![16BIT 30MIPS DSPIC, 30F2010, DIP28](/photos/19/0/190081/42268255_sml.jpg)
DSPIC30F2010-30I/SPG
Manufacturer Part Number
DSPIC30F2010-30I/SPG
Description
16BIT 30MIPS DSPIC, 30F2010, DIP28
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheet
1.DSPIC30F2010-30ISPG.pdf
(244 pages)
Specifications of DSPIC30F2010-30I/SPG
Core Frequency
30MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Operating Temperature Range
-40°C To
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.4
The digital noise filter section is responsible for reject-
ing noise on the incoming capture or quadrature sig-
nals. Schmitt Trigger inputs and a three-clock cycle
delay filter combine to reject low level noise and large,
short duration noise spikes that typically occur in noise
prone applications, such as a motor system.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been
registered for three consecutive clock cycles.
For the QEA, QEB and INDX pins, the clock divide fre-
quency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>) and are derived from
the base instruction cycle T
To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for
all channels is disabled on POR and BOR.
14.5
When the QEI module is not configured for the QEI
mode QEIM<2:0> = 001, the module can be configured
as a simple 16-bit timer/counter. The setup and control
of the auxiliary timer is accomplished through the
QEICON SFR register. This timer functions identically
to Timer1. The QEA pin is used as the timer clock input.
When configured as a timer, the POSCNT register
serves as the Timer Count Register and the MAXCNT
register serves as the Period Register. When a timer/
period register match occur, the QEI interrupt flag will
be asserted.
The only exception between the general purpose tim-
ers and this timer is the added feature of external Up/
Down input select. When the UPDN pin is asserted
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.
The UPDN control/status bit (QEICON<11>) can be
used to select the count direction state of the Timer reg-
ister. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.
2004 Microchip Technology Inc.
Note:
Programmable Digital Noise
Filters
Alternate 16-bit Timer/Counter
Changing the operational mode (i.e., from
QEI to Timer or vice versa), will not affect
the
contents.
Timer/Position
CY
.
Count
Advance Information
Register
In addition, control bit UPDN_SRC (QEICON<0>)
determines whether the timer count direction state is
based on the logic state, written into the UPDN control/
status bit (QEICON<11>), or the QEB pin state. When
UPDN_SRC = 1, the timer count direction is controlled
from the QEB pin. Likewise, when UPDN_SRC = 0, the
timer count direction is controlled by the UPDN bit.
14.6
14.6.1
The QEI module will be halted during the CPU Sleep
mode.
14.6.2
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
14.7
Since the QEI module can function as a quadrature
encoder interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
14.7.1
When the CPU is placed in the Idle mode, the QEI
module will operate if the QEISIDL bit (QEICON<13>)
= 0. This bit defaults to a logic ‘0’ upon executing POR
and BOR. For halting the QEI module during the CPU
Idle mode, QEISIDL should be set to ‘1’.
Note:
QEI Module Operation During CPU
Sleep Mode
QEI Module Operation During CPU
Idle Mode
This Timer does not support the External
Asynchronous Counter mode of operation.
If using an external clock source, the clock
will automatically be synchronized to the
internal instruction cycle.
QEI OPERATION DURING CPU
SLEEP MODE
TIMER OPERATION DURING CPU
SLEEP MODE
QEI OPERATION DURING CPU IDLE
MODE
dsPIC30F
DS70082E-page 95
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