PIC24FJ256GA106-I/MR Microchip Technology, PIC24FJ256GA106-I/MR Datasheet - Page 27

• Manufacturer Part Number: PIC24FJ256GA106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.10
The verify step involves reading back the code memory
space, and comparing it with the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
The flowchart in
cess. Memory reads occur a single byte at a time, so
two bytes must be read to compare with the word in the
programmer’s buffer. Refer to
Code Memory”
code memory.
FIGURE 3-8:
 2010 Microchip Technology Inc.
Note:
Verify Code Memory and
Configuration Word
No
Because
include the device code protection bit,
code memory should be verified immedi-
ately after writing if code protection is
enabled. This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit in
CW1 has been cleared.
with Post-Increment
with Post-Increment
Set TBLPTR = 0
Read High Byte
Read Low Byte
Word = Expect
for implementation details of reading
code memory
Figure 3-8
verified?
Data?
Does
Start
End
All
VERIFY CODE
MEMORY FLOW
the
Yes
Yes
Configuration
illustrates the verify pro-
Section 3.8 “Reading
No
PIC24FJXXXDA1/DA2/GB2/GA3
Failure,
Report
Error
registers
3.11
The Application ID Word is stored at address,
8007F0h, in executive code memory. To read this
memory location, you must use the SIX control code to
move this program memory location to the VISI
register. Then, the REGOUT control code must be
used to clock the contents of the VISI register out of the
device.
and instruction codes that must be serially transmitted
to the device to perform this operation.
After the programmer has clocked out the Application
ID Word, it must be inspected. If the Application ID has
the value, CCh, the programming executive is resident
in memory and the device can be programmed using
the mechanism described in
Programming – Enhanced
Application ID has any other value, the programming
executive is not resident in memory; it must be loaded
to memory before the device can be programmed. The
procedure for loading the programming executive to
memory is described in
the Programming Executive to
3.12
Exiting Program/Verify mode is done by removing V
from MCLR, as displayed in
requirement for exit is that an interval, P16, should
elapse between the last clock and program signals on
PGECx and PGEDx before removing V
FIGURE 3-9:
MCLR
V
PGEDx
PGECx
DD
Table 3-10
Reading the Application ID Word
Exiting ICSP Mode
provides the corresponding control
PGEDx = Input
EXITING ICSP™ MODE
Section 5.4 “Programming
V
P16
IH
ICSP”. However, if the
Section 4.0 “Device
Figure
Memory”.
P17
V
IH
DS39970B-page 27
IH
3-9. The only
.
IH