PIC24FJ256GA106-I/MR Microchip Technology, PIC24FJ256GA106-I/MR Datasheet - Page 42

• Manufacturer Part Number: PIC24FJ256GA106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJXXXDA1/DA2/GB2/GA3
5.0
5.1
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
programming executive only sends one response to
the programmer after receiving and processing a
command. The programming executive command set
is described in
Commands”. The response set is described in
Section 5.3 “Programming Executive
5.1.1
The Enhanced ICSP interface is a 2-wire SPI,
implemented using the PGECx and PGEDx pins. The
PGECx pin is used as a clock input pin and the clock
source must be provided by the programmer. The
PGEDx pin is used for sending command data to, and
receiving response data from, the programming
executive.
Data transmits to the device must change on the rising
edge and hold on the falling edge. Data receives from
the device must change on the falling edge and hold on
the rising edge.
All data transmissions are sent MSb first using 16-bit
mode (see
FIGURE 5-1:
DS39970B-page 42
PGECx
Note:
PGEDx
MSb
1
P1B
THE PROGRAMMING
EXECUTIVE
Programming Executive
Communication
P1A
14 13 12 11
Figure
The Programming Executive (PE) can be
located within the following folder within
your
Microchip\MPLAB IDE\REAL ICE and
then
RIPE_01c_xxxxxx.hex.
COMMUNICATION INTERFACE
AND PROTOCOL
2
Section 5.2 “Programming Executive
3
P1
5-1).
installation
4
select
PROGRAMMING
EXECUTIVE SERIAL
TIMING FOR DATA
RECEIVED FROM DEVICE
5
...
6
the
5
11
of
4
P2
12
Hex
MPLAB
3
13
Responses”.
2
14
P3
PE
1
®
15 16
LSb
IDE:
file:
FIGURE 5-2:
Since a 2-wire SPI is used, and data transmissions are
half-duplex, a simple protocol is used to control the
direction of PGEDx. When the programmer completes
a command transmission, it releases the PGEDx line
and allows the programming executive to drive this line
high. The programming executive keeps the PGEDx
line high to indicate that it is processing the command.
After the programming executive has processed the
command, it brings PGEDx low for 15 s to indicate to
the programmer that the response is available to be
clocked out. The programmer can begin to clock out the
response, 23 s after PGEDx is brought low, and it must
provide the necessary amount of clock pulses to receive
the entire response from the programming executive.
After the entire response is clocked out, the program-
mer should terminate the clock on PGECx until it is time
to send another command to the programming
executive. See
5.1.2
In Enhanced ICSP mode, the PIC24FJXXXDA1/DA2/
GB2/GA3 devices operate from the Internal Fast RC
Oscillator (FRCDIV), which has a nominal frequency of
8 MHz. This oscillator frequency yields an effective
system clock frequency of 4 MHz. To ensure that the
programmer does not clock too fast, it is recommended
that a 4 MHz clock be provided by the programmer.
PGEDx
PGECx
MSb
1
P1B
P1A
SPI RATE
2
14 13 12 11
Figure 5-3
3
P1
4
PROGRAMMING
EXECUTIVE SERIAL TIMING
FOR DATA TRANSMITTED
TO DEVICE
5
 2010 Microchip Technology Inc.
for this protocol.
6
...
11
5
P2
12
4
13
3
14
2
P3
15 16
1
LSb