PIC24FJ256GA106-I/MR Microchip Technology, PIC24FJ256GA106-I/MR Datasheet - Page 29

• Manufacturer Part Number: PIC24FJ256GA106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.0
This section discusses programming the device
through Enhanced ICSP and the programming execu-
tive. The programming executive resides in executive
memory (separate from code memory) and is executed
when Enhanced ICSP Programming mode is entered.
The programming executive provides the mechanism
for the programmer (host device) to program and verify
the PIC24FJXXXDA1/DA2/GB2/GA3 devices, using a
simple command set and communication protocol.
There are several basic functions provided by the
programming executive:
• Read Memory
• Erase Memory
• Program Memory
• Blank Check
• Read Executive Firmware Revision
The programming executive performs the low-level
tasks required for erasing, programming and verifying
a device. This allows the programmer to program the
device by issuing the appropriate commands and data.
Table 4-1
tion for each command is provided in
“Programming Executive
TABLE 4-1:
The programming executive uses the device’s data
RAM for variable storage and program execution. After
the programming executive has run, no assumptions
should be made about the contents of data RAM.
4.1
Figure 4-1
programming process. After entering Enhanced ICSP
mode, the programming executive is verified. Next, the
device is erased. Then, the code memory is
programmed, followed by the configuration locations.
Code memory (including the Configuration registers) is
then verified to ensure that programming was successful.
 2010 Microchip Technology Inc.
SCHECK
READC
READP
PROGP
PROGW
QBLANK
QVER
Command
DEVICE PROGRAMMING –
ENHANCED ICSP
Overview of the Programming
Process
provides the commands. A detailed descrip-
displays the high-level overview of the
Sanity Check
Read Device ID Registers
Read Code Memory
Program One Row of Code Memory
and Verify
Program One Word of Code Memory
and Verify
Query if the Code Memory is Blank
Query the Software Version
COMMAND SET SUMMARY
Commands”.
Description
PIC24FJXXXDA1/DA2/GB2/GA3
Section 5.2
After the programming executive has been verified
in memory
PIC24FJXXXDA1/DA2/GB2/GA3
programmed using the command set provided in
Table
FIGURE 4-1:
4.2
Before programming can begin, the programmer must
confirm that the programming executive is stored in
executive memory. The procedure for this task is
displayed in
First, ICSP mode is entered. Then, the unique
Application ID Word stored in executive memory is
read. If the programming executive is resident, the
Application ID Word is CCh, which means programming
can resume as normal. However, if the Application ID
Word is not CCh, the programming executive must be
programmed to executive code memory using the
method described in
Programming Executive to
Section 3.0 “Device Programming – ICSP”
the ICSP programming method.
the Application ID Word”
reading the Application ID Word in ICSP mode.
4-1.
Confirming the Presence of the
Programming Executive
Figure
(or
Program Configuration Bits
Verify Configuration Bits
Enter Enhanced ICSP™
HIGH-LEVEL ENHANCED
ICSP™ PROGRAMMING FLOW
Exit Enhanced ICSP
loaded
Program Memory
4-2.
Verify Program
Perform Chip
Section 5.4 “Programming the
Erase
Start
End
describes the procedure for
Memory”.
if
Section 3.11 “Reading
not
families
DS39970B-page 29
present),
describes
can
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be