AD7711ANZ Analog Devices Inc, AD7711ANZ Datasheet - Page 13

• Manufacturer Part Number: AD7711ANZ
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7711ANZ

• Rohs Compliant: YES
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 19.5kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

microprocessor much greater control over the AD7711’s cali-
bration procedure. It also means that the user can verify the
calibration is correct by comparing the coefficients after calibra-
tion with prestored values in E
The AD7711 can be operated in single-supply systems provided
that the analog input voltage does not go more negative than
–30 mV. For larger bipolar signals, a V
the part. For battery operation, the AD7711 also offers a pro-
grammable standby mode that reduces idle power consumption
to typically 7 mW.
THEORY OF OPERATION
The general block diagram of a sigma-delta ADC is shown in
Figure 4. It contains the following elements:
∑ A sample-hold amplifier.
∑ A differential amplifier or subtracter.
∑ An analog low-pass filter.
∑ A 1-bit A/D converter (comparator).
∑ A 1-bit DAC.
∑ A digital low-pass filter.
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, which samples the difference
signal at a frequency many times that of the analog signal sampling
frequency (oversampling).
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC,
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7711 samples the input signal at a frequency of 39 kHz or
greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies outside the bandwidth of interest. The noise perfor-
mance is thus improved from this 1-bit level to the performance
outlined in Tables I and II and in Figure 2.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data-word using a
digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first-order sigma-
delta ADC is shown in Figure 5. This contains only a first-order
REV.G
S/H AMP
SNR = (6.02 ¥ number of bits + 1.76) dB,
Figure 4. General Sigma-Delta ADC
+
–
LOW-PASS
ANALOG
FILTER
DAC
2
PROM.
COMPARATOR
SS
of –5 V is required by
DIGITAL
DIGITAL
FILTER
DATA
–13–
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices, charge-balancing ADCs.
The device consists of a differential amplifier (whose output is
the difference between the analog input and the output of a
1-bit DAC), an integrator, and a comparator. The term charge-
balancing comes from the fact that this system is a negative
feedback loop that tries to keep the net charge on the integrator
capacitor at zero, by balancing charge injected by the input
voltage with charge injected by the 1-bit DAC. When the analog
input is zero, the only contribution to the integrator output
comes from the 1-bit DAC. For the net charge on the integrator
capacitor to be zero, the DAC output must spend half its time at
+FS and half its time at –FS. Assuming ideal components, the
duty cycle of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7711 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up, or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.
Input Sample Rate
The modulator sample frequency for the device remains at
f
selected gain. However, gains greater than ¥1 are achieved by a
combination of multiple input samples per modulator cycle and
scaling the ratio of reference capacitor to input capacitor. As a
result of the multiple sampling, the input sample rate of
the device varies with the selected gain (see Table III). The
effective input impedance is 1/C ¥ f
pling capacitance and f
Gain
1
2
4
8
16
32
64
128
DIGITAL FILTERING
The AD7711’s digital filter behaves like a similar analog filter,
with a few minor differences.
CLK IN
/512 (19.5 kHz @ f
Table III. Input Sampling Frequency vs. Gain
Figure 5. Basic Charge-Balancing ADC
V
IN
DIFFERENTIAL
AMPLIFIER
f
2 ¥ f
4 ¥ f
8 ¥ f
8 ¥ f
8 ¥ f
8 ¥ f
8 ¥ f
Input Sampling Frequency (f
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
S
/256 (39 kHz @ f
is the input sample rate.
CLK IN
/256 (78 kHz @ f
/256 (156 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
INTEGRATOR
+FS
–FS
= 10 MHz) regardless of the
DAC
S
where C is the input sam-
COMPARATOR
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
AD7711
= 10 MHz)
S
)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
2