AD7711ANZ Analog Devices Inc, AD7711ANZ Datasheet - Page 20

• Manufacturer Part Number: AD7711ANZ
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7711ANZ

• Rohs Compliant: YES
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 19.5kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Self-Clocking Mode
The AD7711 is configured for its self-clocking mode by tying
the MODE pin high. In this mode, the AD7711 provides the
serial clock signal used for the transfer of data to and from the
AD7711. This self-clocking mode can be used with processors
that allow an external device to clock their serial port, including
most digital signal processors and microcontrollers such as the
68HC11 and 68HC05. It also allows easy interfacing to serial-
parallel conversion circuits in systems with parallel data commu-
nication, allowing interfacing to 74XX299 universal shift
registers without any additional decoding. In the case of shift
registers, the serial clock line should have a pull-down resistor
instead of the pull-up resistor shown in Figures 10 and 11.
Read Operation
Data can be read from either the output register, the control
register, or the calibration registers. A0 determines whether the
data read accesses data from the control register or from the
output/calibration registers. This A0 signal must remain valid
for the duration of the serial read operation. With A0 high, data
is accessed from either the output register or the calibration
registers. With A0 low, data is accessed from the control register.
The function of the DRDY line is dependent only on the output
update rate of the device and the reading of the output data
register. DRDY goes low when a new data-word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the DRDY line re-
mains low. The output register continues to be updated at the
output update rate but DRDY will not indicate this. A read
from the device in this circumstance accesses the most recent
word in the output register. If a new data-word becomes available
to the output register while data is being read from the output
register, DRDY will not indicate this and the new data-word
will be lost to the user. DRDY is not affected by reading from
the control register or the calibration registers.
AD7711
SDATA (O)
DRDY (O)
SCLK (O)
RFS (I)
A0 (I)
Figure 10. Self-Clocking Mode, Output Data Read Operation
t
2
t
4
t
6
t
7
MSB
t
8
–20–
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low with DRDY high, no data trans-
fer takes place. DRDY does not have any effect on reading data
from the control register or from the calibration registers.
Figure 10 shows a timing diagram for reading from the AD7711
in the self-clocking mode. The read operation shows a read from
the AD7711’s output data register. A read from the control
register or calibration registers is similar, but, in these cases, the
DRDY line is not related to the read function. Depending on
the output update rate, it can go low at any stage in the control/
calibration register read cycle without affecting the read, and its
status should be ignored. A read operation from either the con-
trol or calibration registers must always read 24 bits of data
from the respective register.
Figure 10 shows a read operation from the AD7711. For the
timing diagram shown, it is assumed that there is a pull-up
resistor on the SCLK output. With DRDY low, the RFS
input is brought low. RFS going low enables the serial clock of
the AD7711 and also places the MSB of the word on the serial
data line. All subsequent data bits are clocked out on a high to
low transition of the serial clock and are valid prior to the follow-
ing rising edge of this clock. The final active falling edge of
SCLK clocks out the LSB, and this LSB is valid prior to the final
active rising edge of SCLK. Coincident with the next falling
edge of SCLK, DRDY is reset high. DRDY going high turns off
the SCLK and the SDATA outputs, which means the data hold
time for the LSB is slightly shorter than for all other bits.
t
9
t
10
LSB
THREE-STATE
t
3
t
5
REV. G