AD7711ANZ Analog Devices Inc, AD7711ANZ Datasheet - Page 7

• Manufacturer Part Number: AD7711ANZ
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7711ANZ

• Rohs Compliant: YES
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 19.5kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Mnemonic
10
11
12
13
14
15
16
17
18
19
REV.G
1
2
3
4
5
6
7
8
9
SCLK
MCLK IN
MCLK OUT
A0
SYNC
MODE
AIN1(+)
AIN1(–)
RTD1
RTD2
V
AV
V
REF IN(–)
REF IN(+)
REF OUT
AIN2
AGND
TFS
SS
BIAS
DD
Function
Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes
active when RFS or TFS goes low, and goes high impedance when either RFS or TFS returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7711 in smaller batches of data.
Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can
be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.
When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
Address Input. With this input low, reading and writing to the device is to the control register. With this input
high, access is to either the data register or the calibration registers.
Logic Input. Allows for synchronization of the digital filters when using a number of AD7711s. It resets
the nodes of the digital filter.
Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its
external clocking mode.
Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input
is connected to an output current source that can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.
Analog Input Channel 1. Negative input of the programmable gain differential analog input.
Constant Current Output. A nominal 200 mA constant current is provided at this pin; this current can be
used as the excitation current for RTDs. This current can be turned on or off via the control register.
Constant Current Output. A nominal 200 mA constant current is provided at this pin; this current can be
used as the excitation current for RTDs. This current can be turned on or off via the control register, and
can be used to eliminate lead resistance errors in 3-wire RTD configurations.
Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1
or AIN2 should not go > 30 mV negative w.r.t. V
Analog Positive Supply Voltage, 5 V to 10 V.
Input Bias Voltage. This input voltage should be set such that V
¥ V
and V
V
Reference Input. The REF IN(–) can lie anywhere between AV
than REF IN(–).
Reference Input. The reference input is differential provided REF IN(+) is greater than REF IN(–).
REF IN(+) can lie anywhere between AV
Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output
that is referred to AGND. It is a buffered output capable of providing 1 mA to an external load.
Analog Input Channel 2. Single-ended programmable gain analog input.
Ground Reference Point for Analog Circuitry.
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial
data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after TFS goes low. During a write operation to the AD7711, the SDATA line should not return to high
impedance until after TFS returns high.
SS
REF
= –5 V, it can be tied to AGND; with AV
SS
> V
. Thus with AV
SS
where V
REF
PIN FUNCTION DESCRIPTIONS
DD
is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV
= 5 V and V
–7–
SS
DD
= 0 V, it can be tied to REF OUT; with AV
and V
DD
= 10 V, it can be tied to 5 V.
SS
SS
for correct operation of the device.
.
BIAS
DD
+ 0.85 ¥ V
and V
SS
provided REF IN(+) is greater
REF
< AV
DD
DD
and V
AD7711
= +5 V and
BIAS
– 0.85
DD
2