AD7711ANZ Analog Devices Inc, AD7711ANZ Datasheet - Page 16

• Manufacturer Part Number: AD7711ANZ
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7711ANZ

• Rohs Compliant: YES
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 19.5kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IN(+) pin. This REF OUT pin is a single-ended output, refer-
enced to AGND, which is capable of providing up to 1 mA to
an external load. In applications where REF OUT is connected
directly to REF IN(+), REF IN(–) should be tied to AGND to
provide the nominal 2.5 V reference for the AD7711.
The reference inputs of the AD7711, REF IN(+) and REF IN(–),
provide a differential reference input capability. The common-
mode range for these differential inputs is from V
The nominal differential voltage, V
is 2.5 V for specified operation, but the reference voltage can go
to 5 V with no degradation in performance if the absolute value
of REF IN(+) and REF IN(–) does not exceed its AV
V
The part is also functional with V
degraded performance because the output noise will, in terms
of LSB size, be larger. REF IN(+) must always be greater than
REF IN(–) for correct operation of the AD7711.
Both reference inputs provide a high impedance, dynamic load
similar to the analog inputs. The maximum dc input leakage
current is 10 pA (± 1 nA over temperature), and source resis-
tance may result in gain errors on the part. The reference inputs
look like the analog input (see Figure 7). In this case, R
5 kW typ and C
f
is 20 pF; for a gain of 16, it is 10 pF; for a gain of 32, it is 5 pF; for
a gain of 64, it is 2.5 pF; and for a gain of 128, it is 1.25 pF.
The digital filter of the AD7711 removes noise from the refer-
ence input just as it does with the analog input, and the same
limitations apply regarding lack of noise rejection at integer
multiples of the sampling frequency. The output noise perfor-
mance outlined in Tables I and II assumes a clean reference. If
the reference noise in the bandwidth of interest is excessive, it
can degrade the performance of the AD7711. Using the on-chip
reference as the reference source for the part (connecting
REF OUT to REF IN) results in degraded output noise perfor-
mance from the AD7711 for portions of the noise table that are
dominated by the device noise. The on-chip reference noise
effect is eliminated in ratiometric applications where the refer-
ence is used to provide the excitation voltage for the analog
front end. The connection shown in Figure 8 is recommended
when using the on-chip reference. Recommended reference
voltage sources for the AD7711 include the AD580 and AD680
2.5 V references.
V
The V
circuitry is biased. It essentially provides the return path for
analog currents flowing in the modulator and, as such, it should
be driven from a low impedance point to minimize errors.
AD7711
CLK IN
BIAS
SS
limits and the V
Input
BIAS
/256 and does not vary with gain. For gains of 1 to 8, C
input determines at what voltage the internal analog
Figure 8. REF OUT/REF IN Connection
INT
varies with gain. The input sample rate is
BIAS
AD7711
REF OUT
input voltage range limits are obeyed.
REF
REF IN(+)
REF IN(–)
REF
voltages down to 1 V but with
(REF IN(+) – REF IN(–)),
SS
to AV
DD
INT
and
DD
is
.
INT
–16–
For maximum internal headroom, the V
set halfway between AV
AV
headroom the circuit has at the upper end, while the difference
between V
of headroom the circuit has at the lower end. When choosing a
V
single 5 V operation, the selected V
V
V
AV
tion, the selected V
V
itself is greater than V
example, with AV
allowable range for the V
AV
is 4.25 V to 5.25 V. With AV
and V
The V
ply rejection performance of the AD7711. If the V
tracks the AV
from the AV
external Zener diode connected between the AV
V
in AV
USING THE AD7711
SYSTEM DESIGN CONSIDERATIONS
The AD7711 operates differently from successive approxima-
tion ADCs or integrating ADCs. Because it samples the signal
continuously, like a tracking ADC, there is no need for a start
convert command. The output register is updated at a rate
determined by the first notch of the filter, and the output can
be read at any time, either synchronously or asynchronously.
Clocking
The AD7711 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be connected
between MCLK IN and MCLK OUT, in which case the clock
circuit will function as a crystal-controlled oscillator. For lower
clock frequencies, a ceramic resonator may be used instead of
the crystal. For these lower frequency oscillators, external
capacitors may be required on either the ceramic resonator or
on the crystal.
The input sampling frequency, the modulator sampling frequency,
the –3 dB frequency, the output update rate, and the calibration
time are all directly related to the master clock frequency,
f
halve the above frequencies and update rate and will double the
calibration time.
The current drawn from the DV
related to f
DV
AV
System Synchronization
If multiple AD7711s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the SYNC input resets the filter and
CLK IN.
BIAS
BIAS
BIAS
REF
BIAS
DD
DD
DD
DD
DD
does not exceed AV
DD
voltage, ensure that it stays within prescribed limits. For
± 0.85 ¥ V
voltage itself is greater than V
REF
as the source for the V
BIAS
and (V
– 2.1 V. For single 10 V operation or dual ± 5 V opera-
= 9.5 V, V
power supply.
current but will not affect the current drawn from the
Reducing the master clock frequency by a factor of 2 will
power supply rejection performance.
= +2.5 V, the V
SS
voltage does have an effect on the AV
CLK IN
DD
and (V
BIAS
DD
supply line from 80 dB to 95 dB. Using an
. Reducing f
REF
supply, it improves the power supply rejection
DD
SS
+ 0.85 ¥ V
BIAS
= 0 V, and V
BIAS
= 4.75 V, V
does not exceed AV
SS
voltage must ensure that V
DD
+ 3 V or less than AV
BIAS
– 0.85 ¥ V
DD
BIAS
and V
BIAS
REF
or V
voltage is 2.125 V to 2.625 V. With
CLK IN
range is –2.625 V to +2.625 V.
DD
) determines the amount of
SS
DD
REF
voltage gives the improvement
SS
SS
= +4.75 V, V
= 0 V, and V
. The difference between
REF
by a factor of 2 will halve the
BIAS
or that the V
SS
power supply is also directly
= 5 V, the range for V
+ 2.1 V and less than
) determines the amount
voltage must ensure that
BIAS
DD
or V
voltage should be
DD
REF
SS
SS
BIAS
DD
DD
– 3 V. For
= –4.75 V,
BIAS
BIAS
= 2.5 V, the
or that the
power sup-
line and
voltage
¥ 0.85 ¥
voltage
REV. G
BIAS