AD7711ANZ Analog Devices Inc, AD7711ANZ Datasheet - Page 17

• Manufacturer Part Number: AD7711ANZ
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7711ANZ

• Rohs Compliant: YES
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 19.5kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

places the AD7711 into a consistent, known state. A common
signal to the AD7711s’ SYNC inputs will synchronize their
operation. This would typically be done after each AD7711 has
performed its own calibration or has had calibration coefficients
loaded to it.
The SYNC input can also be used to reset the digital filter in
systems where the turn-on time of the digital power supply
(DV
ing internally before the DV
operating level, 4.75 V. With a low DV
AD7711’s internal digital filter logic does not operate correctly.
Thus, the AD7711 may have clocked itself into an incorrect
operating condition by the time DV
level. The digital filter is reset upon issue of a calibration com-
mand (whether it is self-calibration, system calibration, or back-
ground calibration) to the AD7711. This ensures correct
operation of the AD7711. In systems where the power-on de-
fault conditions of the AD7711 are acceptable, and no calibra-
tion is performed after power-on, issuing a SYNC pulse to the
AD7711 resets the AD7711’s digital filter logic. An R, C on the
SYNC line, with R, C time constant longer than the DV
power-on time, performs the SYNC function.
Accuracy
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance. The AD7711 achieves excellent
linearity by the use of high quality, on-chip silicon dioxide capaci-
tors, which have a very low capacitance/voltage coefficient. The
device also achieves low input drift through the use of chopper
stabilized techniques in its input stage. To ensure excellent
performance over time and temperature, the AD7711 uses digital
calibration techniques that minimize offset and gain error.
Autocalibration
Autocalibration on the AD7711 removes offset and gain errors
from the device. A calibration routine should be initiated on the
device whenever there is a change in the ambient operating
temperature or supply voltage. It should also be initiated if there
is a change in the selected gain, filter notch, or bipolar/unipolar
input range. However, if the AD7711 is in background calibra-
tion mode, these changes are taken care of automatically (after
the settling time of the filter has been allowed for).
The AD7711 offers self-calibration, system calibration, and
background calibration facilities. For calibration to occur on
the selected channel, the on-chip microcontroller must record
the modulator output for two different input conditions. These
are zero-scale and full-scale points. With these readings, the
microcontroller can calculate the gain slope for the input-to-
output transfer function of the converter. Internally, the part
works with a resolution of 33 bits to determine its conversion
result of either 16 bits or 24 bits.
The AD7711 also provides the facility to write to the on-chip
calibration registers, and in this manner, the span and offset for
the part can be adjusted by the user. The offset calibration regis-
ter contains a value that is subtracted from all conversion
results, while the full-scale calibration register contains a value
that is multiplied by all conversion results. The offset calibration
coefficient is subtracted from the result prior to the multiplica-
tion by the full-scale coefficient. In the first three modes outlined
here, the DRDY line indicates that calibration is complete by
REV.G
DD
) is very long. In such cases, the AD7711 starts operat-
DD
line has reached its minimum
DD
has reached its correct
DD
voltage, the
DD
–17–
going low. If DRDY is low before (or goes low during) the cali-
bration command, it may take up to one modulator cycle before
DRDY goes high to indicate that calibration is in progress.
Therefore, DRDY should be ignored for up to one modulator
cycle after the last bit of the calibration command is written to
the control register.
Self-Calibration
In the self-calibration mode with a unipolar input range, the
zero-scale point used in determining the calibration coefficients
is with both inputs shorted (that is, AIN1(+) = AIN1(–) =
V
point is V
verting an internal shorted input node. The full-scale coefficient
is determined from the span between this shorted input conver-
sion and a conversion on an internal V
calibration mode is invoked by writing the appropriate values
(0, 0, 1) to the MD2, MD1, and MD0 bits of the control regis-
ter. In this calibration mode, the shorted input node is switched
into the modulator first and a conversion is performed; the V
node is then switched in and another conversion is performed.
When the calibration sequence is complete, the calibration coeffi-
cients updated, and the filter resettled to the analog input voltage,
the DRDY output goes low. The self-calibration procedure takes
into account the selected gain on the PGA.
For bipolar input ranges in the self-calibrating mode, the sequence
is very similar to that just outlined. In this case, the two points
that the AD7711 calibrates are midscale (bipolar zero) and
positive full scale.
System Calibration
System calibration allows the AD7711 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self-
calibration but uses voltage values presented by the system to
the AIN inputs for the zero- and full-scale points. System
calibration is a two-step process. The zero-scale point must
be presented to the converter first. It must be applied to the
converter before the calibration step is initiated and must
remain stable until the step is complete. System calibration is
initiated by writing the appropriate values (0, 1, 0) to the MD2,
MD1, and MD0 bits of the control register. The DRDY output
from the device signals when the step is complete by going low.
After the zero-scale point is calibrated, the full-scale point is
applied and the second step of the calibration process is initiated
by again writing the appropriate values (0, 1, 1) to MD2, MD1,
and MD0. Again the full-scale voltage must be set up before the
calibration is initiated, and it must remain stable throughout the
calibration step. DRDY goes low at the end of this second step to
indicate that the system calibration is complete. In the unipolar
mode, the system calibration is performed between the two end-
points of the transfer function; in the bipolar mode, it is performed
between midscale and positive full scale.
This two-step system calibration mode offers another feature.
After the sequence has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the zero
reference point or the system gain. This is achieved by perform-
ing the first step of the system calibration sequence (by writing
0, 1, 0 to MD2, MD1, MD0). This adjusts the zero-scale or
offset point but does not change the slope factor from that set
during a full system calibration sequence.
BIAS
for AIN1 and AIN2 = V
REF
. The zero-scale coefficient is determined by con-
BIAS
for AIN2), and the full-scale
REF
node. The self-
AD7711
REF
2