AD7711ANZ Analog Devices Inc, AD7711ANZ Datasheet - Page 14

• Manufacturer Part Number: AD7711ANZ
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7711ANZ

• Rohs Compliant: YES
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 19.5kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise super-
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this, and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7711 has
overrange headroom built into the sigma-delta modulator and
digital filter, which allows overrange excursions of 5% above the
analog input range. If noise signals are larger than this, consid-
eration should be given to analog input filtering, or to reducing
the input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
Filter Characteristics
The cutoff frequency of the digital filter is determined by the
value loaded to Bits FS0 to FS11 in the control register. At the
maximum clock frequency of 10 MHz, the minimum cutoff
frequency of the filter is 2.58 Hz while the maximum program-
mable cutoff frequency is 269 Hz.
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 2.62 Hz, which corresponds to a first filter notch fre-
quency of 10 Hz. This is a (sinx/x)
that provides >100 dB of 50 Hz and 60 Hz rejection. Program-
ming a different cutoff frequency via FS0–FS11 does not alter
the profile of the filter response; it changes the frequency of the
notches as outlined in the Control Register section.
Since the AD7711 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data on the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
equates to this filter notch frequency and the settling time of the
filter to a full-scale step input is four times the output data
period. In applications using both input channels, the settling
time of the filter must be allowed to elapse before data from
the second channel is accessed.
Post Filtering
The on-chip modulator provides samples at a 19.5 kHz output
rate. The on-chip digital filter decimates these samples to provide
data at an output rate that corresponds to the programmed first
AD7711
Figure 6. Frequency Response of AD7711 Filter
–100
–120
–140
–160
–180
–200
–220
–240
–20
–40
–60
–80
0
0
10
20
FREQUENCY – Hz
30
3
response (also called sinc
40
50
60
3
)
–14–
notch frequency of the filter. Since the output data rate ex-
ceeds the Nyquist criterion, the output rate for a given band-
width will satisfy most application requirements. However,
there may be some applications that require a higher data rate
for a given bandwidth and noise performance. Applications
that need this higher data rate will require some post filtering
following the digital filter of the AD7711.
For example, if the required bandwidth is 7.86 Hz but the required
update rate is 100 Hz, the data can be taken from the AD7711
at the 100 Hz rate giving a –3 dB bandwidth of 26.2 Hz. Post
filtering can be applied to this to reduce the bandwidth and
output noise to the 7.86 Hz bandwidth level, while maintaining
an output rate of 100 Hz.
Post filtering can also be used to reduce the output noise from
the device for bandwidths below 2.62 Hz. At a gain of 128, the
output rms noise is 250 nV. This is essentially device noise or
white noise, and since the input is chopped, the noise has a flat
frequency response. By reducing the bandwidth below 2.62 Hz,
the noise in the resultant pass band can be reduced. A reduction
in bandwidth by a factor of 2 results in a ÷2 reduction in the
output rms noise. This additional filtering will result in a longer
settling time.
Antialias Considerations
The digital filter does not provide any rejection at integer mul-
tiples of the modulator sample frequency (n ¥ 19.5 kHz, where
n = 1, 2, 3 . . . ). This means that there are frequency bands,
±f
where noise passes unattenuated to the output. However, due to
the AD7711’s high oversampling ratio, these bands occupy only
a small fraction of the spectrum, and most broadband noise is
filtered. In any case, because of the high oversampling ratio a
simple, RC, single-pole filter is generally sufficient to attenuate
the signals in these bands on the analog input and thus provide
adequate antialiasing filtering.
If passive components are placed in front of the AD7711, care
must be taken to ensure that the source impedance is low enough
so as not to introduce gain errors in the system. The dc input
impedance for the AD7711 is over 1 GW. The input appears as
a dynamic load that varies with the clock frequency and with the
selected gain (see Figure 7). The input sample rate, as shown
in Table III, determines the time allowed for the analog input
capacitor, C
longer charge time for this capacitor, which may result in gain
errors being introduced on the analog inputs. Table IV shows the
allowable external resistance/capacitance values such that no
gain error to the 16-bit level is introduced while Table V shows
the allowable external resistance/capacitance values such that no
gain error to the 20-bit level is introduced. Both inputs of the
differential input channel (AIN1) look into similar input circuitry.
3 dB
wide (f
IN
3 dB
AIN
Figure 7. Analog Input Impedance
, to be charged. External impedances result in a
is the cutoff frequency selected by FS0 to FS11),
SWITCHING FREQUENCY DEPENDS
ON
f
CLKIN
11.5pF TYP
7k
AND SELECTED GAIN
R
INT
TYP
C
INT
V
BIAS
AD7711
IMPEDANCE
>1G
HIGH
REV. G